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MVME2400 VPD Reference Information
http://www.mcg.mot.com/literature B-11
B
77 (0x4D) 37
78 (0x4E) 35
79 (0x4F) 30
80 (0x50) 0A
PACKET
INTEGER
EPROM CRC
When computing the CRC this field (i.e 4 bytes) is
set to zero.This CRC only covers the range as Inte-
ger (4-byte). Note:
Lower CRC byte for the calculation of CRC = 00
Upper CRC byte for the calculation of CRC =
255
81 (0x51) 04
82 (0x52) xx
** CRC to be filled in at ATE
83 (0x53) xx
84 (0x54) xx
85 (0x55) xx
86 (0x56) OB
PACKET
BINARY
FLASH Memory Configuration #1
87 (0x57) 0A
88 (0x58) 00
89 (0x59) 01
90 (0x5A) 22
91 (0x5B) C4
92 (0x5C) 10
93 (0x5D) 04
94 (0x5E) 02
95 (0x5F) 20
96 (0x60) 20
97 (0x61) 00
98 (0x62) OB
PACKET
BINARY
FLASH Memory Configuration #2
99 (0x63) 0A
Table B-5. VPD SROM Configuration Specification for 01-W3394F01*
OFFSET VALUE FIELD TYPE DESCRIPTION
- MVME2400-Series 1
- VME Processor Module 1
- Programmer’s 1
- Reference Guide 1
- Restricted Rights Legend 2
- ©Copyright Motorola 1999 4
- All Rights Reserved 4
- March 1999 4
- Safety Summary 5
- Safety Depends On You 5
- Contents 7
- Glossary 14
- List of Figures 15
- List of Tables 17
- 1Board Description and 21
- Memory Maps 21
- Overview 23
- Feature Summary 23
- System Block Diagram 24
- 2067 9708 26
- Configuration 36
- PCI MEMORYPROCESSOR 42
- PCI Memory 44
- Processor 44
- ISA Space 44
- PCI I/O Space 44
- ISA Local Resource Bus 49
- VME Registers 51
- Introduction 59
- ❏ Interrupt Controller 60
- Block Diagram 61
- PPC Bus Interface 63
- ❏ HAWK (Highest Priority) 74
- ❏ CPUy (Lowest Priority) 74
- PCI Bus Interface 76
- ❏ Memory and I/O 87
- ❏ Configuration 87
- ❏ Special Cycle 87
- ❏ Interrupt Acknowledge 87
- PPC Address + Offset 88
- PCI Address 88
- 0 0 0 0 0 0 0 88
- Endian Conversion 95
- 1916 9610 96
- Error Handling 98
- Watchdog Timers 99
- PCI/PPC Contention Handling 102
- Functional Description 103
- Transaction Ordering 104
- PHB Hardware Configuration 106
- External Interrupt Interface 108
- Architecture 108
- CSR’s Readability 109
- Interrupt Source Priority 109
- Nesting of Interrupt Events 110
- Spurious Vector Generation 110
- 8259 Compatibility 111
- PHB Detected Errors 111
- Interrupt Delivery Modes 112
- Block Diagram Description 113
- Programming Notes 118
- Operation 120
- Architectural Notes 121
- Registers 123
- MBT Time Out Length 128
- 00 256 µsec 128
- 01 64 µsec 128
- 10 8 µsec 128
- 11 disabled 128
- PCI Registers 153
- $CFB $CFA $CF9 $CF8 162
- $CF8 $CF9 $CFA $CFB 162
- MPIC Registers 166
- Timer 0 - $01100 176
- Timer 0 - $01120 178
- Processor 0 $20080 184
- 3System Memory Controller 187
- Block Diagrams 188
- PowerPC 60x Bus 189
- SDRAMPowerPC 190
- Side Side 190
- PowerPC 60x Bus Interface 199
- ROM/Flash Interface 204
- I2C Interface 209
- Refresh/Scrub 221
- CSR Accesses 221
- External Register Set 221
- Chip Configuration 221
- Programming Model 222
- Table 3-9. Register Summary 223
- ERR_SYNDROME 236
- SBE_COUNT 236
- ERROR_ADDRESS 238
- I2_DATARD 252
- Software Considerations 262
- Possible Control Bit Values 266
- ECC Codes 274
- 4Universe II (VMEbus to PCI) 277
- Registers (UCSR) 283
- Universe II Register Map 284
- Register Name 285
- LSI0_TO 285
- LSI1_TO 286
- LSI2_TO 286
- LSI3_TO 286
- VSI0_TO 288
- VSI1_TO 288
- VSI2_TO 288
- VSI3_TO 288
- VCSR_TO 289
- 5Programming Details 291
- Interrupt Handling 292
- Hawk MPIC 293
- 8259 Interrupts 294
- ISA DMA Channels 297
- Exceptions 298
- Soft Reset 299
- Endian Issues 301
- Figure 5-3. Big-Endian Mode 302
- PCI Local Bus 302
- 60X System Bus 302
- Processor/Memory Domain 304
- MPIC’s Involvement 304
- PCI Domain 304
- Universe II’s Involvement 305
- VMEbus Domain 305
- ROM/Flash Initialization 306
- Ordering Related 307
- Documentation 307
- Manufacturers’ Documents 308
- Publication 309
- Document Title and Source 309
- Related Specifications 311
- MVME2400 VPD Reference 315
- Information 315
- Field Size 319
- VPD data packet 320
- Example VPD SROM 322
- Numerics 341
- 2-87, 2-89 348
- Programmer’s Reference Guide 353
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