Motorola MVME2400 Series Wartungshandbuch PDF herunterladen (Seite 256)

100

101

3-70 Computer Group Literature Center Web Site

System Memory Controller (SMC)

trc0,1,2 Together trc0,1,2 determine the minimum number of clock

cycles that the SMC assumes the SDRAM requires to satisfy its

Trc parameter. These bits are encoded as follows:

tras0,1

Together tras0,1 determine the minimum number of clock

cycles that the SMC assumes the SDRAM requires to satisfy its

tRAS parameter. These bits are encoded as follows:

swr_dpl

swr_dpl causes the SMC to always wait until four clocks after

the write command portion of a single write before allowing a

precharge to occur. This function may not be required. If such is

the case, swr_dpl

can be cleared by software.

Table 3-16. Trc Encoding

trc0,1,2 Minimum Clocks for Trc

%000 8

%001 9

%010 10

%011 11

%100 reserved

%101 reserved

%110 6

%111 7

Table 3-17. tras

Encoding

tras0,1 Minimum Clocks for tras

%00 4

%01 5

%10 6

%11 7

1 2 ... 251 252 253 254 255 256 257 258 259 260 261 ... 353 354

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