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Functional Description
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Functional Description
Overview
The MVME2400 series is a family of single-slot VME processor modules.
It consists of the MPC750 processor and L2 cache that directly connects to
the MPC750, the Hawk ASIC, which is made up of the PCI Bridge (PHB),
the Multi-Processor Interrupt Controller (MPIC), and the System Memory
Controller (SMC). The MVME2400 series also includes 9MB of Flash
memory, 32MB to 256MB of ECC-protected SDRAM, and a rich set of
features of I/O peripherals.
The I/O peripheral devices on the PCI bus include: the Universe II
VMEbus interface ASIC, and two PMC slots. Functions provided from the
ISA bus are: one asynchronous serial port, a real-time clock,
counters/timers, and a software-readable header.
The MVME2400 series board interfaces to the VMEbus via the P1 and P2
connectors, which use the 5-row 160-pin connectors as specified in the
proposed VME64 Extension Standard. It also draws +5V, +12V, and -12V
power from the VMEbus backplane through these two connectors.
Additional power of 2.0V and 3.3V is regulated onboard from the +5V
power.
Front panel connectors on the MVME2400 series board include: an RJ45
connector for the Ethernet 10Base-T/100Base-TX interface, and an RJ45
connector for the async serial debug port. The front panel also includes
reset and abort switches and status LEDs.
The MVME2400 series contains two IEEE1386.1 PCI Mezzanine Card
(PMC) slots. These PMC slots are 64-bit capable and support both front
and rear I/O. Pins 1 through 64 of PMC slot 1 connector J14 are routed to
row C and row A of the 5-row DIN P2 connector. Pins 1 through 46 of
PMC slot 2 connector J24 are routed to row D and row Z of P2.
Additional PCI expansion is supported with a 114-pin Mictor connector.
This connection allows stacking of one or two PMCspan dual-PMC carrier
boards, to increase the I/O capability. Each PMCspan board requires an
additional VME slot.
- MVME2400-Series 1
- VME Processor Module 1
- Programmer’s 1
- Reference Guide 1
- Restricted Rights Legend 2
- ©Copyright Motorola 1999 4
- All Rights Reserved 4
- March 1999 4
- Safety Summary 5
- Safety Depends On You 5
- Contents 7
- Glossary 14
- List of Figures 15
- List of Tables 17
- 1Board Description and 21
- Memory Maps 21
- Overview 23
- Feature Summary 23
- System Block Diagram 24
- 2067 9708 26
- Configuration 36
- PCI MEMORYPROCESSOR 42
- PCI Memory 44
- Processor 44
- ISA Space 44
- PCI I/O Space 44
- ISA Local Resource Bus 49
- VME Registers 51
- Introduction 59
- ❏ Interrupt Controller 60
- Block Diagram 61
- PPC Bus Interface 63
- ❏ HAWK (Highest Priority) 74
- ❏ CPUy (Lowest Priority) 74
- PCI Bus Interface 76
- ❏ Memory and I/O 87
- ❏ Configuration 87
- ❏ Special Cycle 87
- ❏ Interrupt Acknowledge 87
- PPC Address + Offset 88
- PCI Address 88
- 0 0 0 0 0 0 0 88
- Endian Conversion 95
- 1916 9610 96
- Error Handling 98
- Watchdog Timers 99
- PCI/PPC Contention Handling 102
- Functional Description 103
- Transaction Ordering 104
- PHB Hardware Configuration 106
- External Interrupt Interface 108
- Architecture 108
- CSR’s Readability 109
- Interrupt Source Priority 109
- Nesting of Interrupt Events 110
- Spurious Vector Generation 110
- 8259 Compatibility 111
- PHB Detected Errors 111
- Interrupt Delivery Modes 112
- Block Diagram Description 113
- Programming Notes 118
- Operation 120
- Architectural Notes 121
- Registers 123
- MBT Time Out Length 128
- 00 256 µsec 128
- 01 64 µsec 128
- 10 8 µsec 128
- 11 disabled 128
- PCI Registers 153
- $CFB $CFA $CF9 $CF8 162
- $CF8 $CF9 $CFA $CFB 162
- MPIC Registers 166
- Timer 0 - $01100 176
- Timer 0 - $01120 178
- Processor 0 $20080 184
- 3System Memory Controller 187
- Block Diagrams 188
- PowerPC 60x Bus 189
- SDRAMPowerPC 190
- Side Side 190
- PowerPC 60x Bus Interface 199
- ROM/Flash Interface 204
- I2C Interface 209
- Refresh/Scrub 221
- CSR Accesses 221
- External Register Set 221
- Chip Configuration 221
- Programming Model 222
- Table 3-9. Register Summary 223
- ERR_SYNDROME 236
- SBE_COUNT 236
- ERROR_ADDRESS 238
- I2_DATARD 252
- Software Considerations 262
- Possible Control Bit Values 266
- ECC Codes 274
- 4Universe II (VMEbus to PCI) 277
- Registers (UCSR) 283
- Universe II Register Map 284
- Register Name 285
- LSI0_TO 285
- LSI1_TO 286
- LSI2_TO 286
- LSI3_TO 286
- VSI0_TO 288
- VSI1_TO 288
- VSI2_TO 288
- VSI3_TO 288
- VCSR_TO 289
- 5Programming Details 291
- Interrupt Handling 292
- Hawk MPIC 293
- 8259 Interrupts 294
- ISA DMA Channels 297
- Exceptions 298
- Soft Reset 299
- Endian Issues 301
- Figure 5-3. Big-Endian Mode 302
- PCI Local Bus 302
- 60X System Bus 302
- Processor/Memory Domain 304
- MPIC’s Involvement 304
- PCI Domain 304
- Universe II’s Involvement 305
- VMEbus Domain 305
- ROM/Flash Initialization 306
- Ordering Related 307
- Documentation 307
- Manufacturers’ Documents 308
- Publication 309
- Document Title and Source 309
- Related Specifications 311
- MVME2400 VPD Reference 315
- Information 315
- Field Size 319
- VPD data packet 320
- Example VPD SROM 322
- Numerics 341
- 2-87, 2-89 348
- Programmer’s Reference Guide 353
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