Motorola MVME2400 Series Wartungshandbuch PDF herunterladen (Seite 254)

3-68 Computer Group Literature Center Web Site

System Memory Controller (SMC)

should begin until after the write is done. A simple way to do this is to

perform at least two read accesses to this or another register before and

after the write.

Additionally, sometime during the envelope, before or after the write, all

of the SDRAMs’ open pages must be closed and the Hawk’s open page

tracker reset. The way to do this is to allow enough time for at least one

SDRAM refresh to occur by waiting for the 32-Bit Counter to increment

at least 100 times. The wait period needs to happen during the envelope.

RAM E/F/G/H BASE

These control bits define the base address for their block’s

SDRAM. RAM E/F/G/H BASE

bits 0-7/8-15/16-23/24-31

correspond to PowerPC60x address bits 0 - 7. For larger

SDRAM sizes, the lower significant bits of RAM E/F/G/H

BASE are ignored. This means that the block’s base address

will always appear at an even multiple of its size. Remember

that bit 0 is MSB.

Note that RAM A/B/C/D BASE

are located at $FEF80018

(refer to the section titled “SDRAM Base Address Register

(Blocks A/B/C/D)” for more information). They operate the

same for blocks A-D as these bits do for blocks E-H.

Also note that the combination of RAM_X_BASE

and

ram_x_siz

should never be programmed such that SDRAM

responds at the same address as the CSR, ROM/Flash,

External Register Set, or any other slave on the PowerPC bus.

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Motorola MVME2400 Series Wartungshandbuch Seite 254