Motorola MVME2400 Series Wartungshandbuch Seite 263

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Software Considerations
http://www.mcg.mot.com/literature 3-77
3
Initializing SDRAM Related Control Registers
In order to establish proper SDRAM operation, software must configure
control register bits in Hawk that affect each SDRAM block’s speed, size,
base address, and enable. The SDRAM speed attributes are the same for all
blocks and are controlled by one 32-bit register. The size, base address and
enable can be different for each block and are controlled in individual 8-
bit registers.
SDRAM Speed Attributes
The SDRAM speed attributes come up from power-up reset initialized to
the slowest settings that Hawk is capable of. This allows SDRAM accesses
to be performed before the SDRAM speed attributes are known. An
example of a need for this is when software requires some working
memory that it can use while gathering and evaluating SDRAM device
data from serial EEPROM’s. Once software knows the SDRAM speed
parameters for all blocks, it should discontinue accessing SDRAM for at
least one refresh period before and after it programs the SDRAM speed
attribute bits.
SDRAM Size
The SDRAM size control bits come up from power-up reset cleared to
zero. Once software has determined the correct size for an SDRAM block,
it should set the block’s size bits to match. The value programmed into the
size bits tells the Hawk how big the block is (for map decoding), and how
to translate that block’s 60x addresses to SDRAM addresses.
Programming a block’s size to non-zero also allows it to participate in
scrubbing if scrubbing is enabled.
After software programs the size bits, it should wait for a refresh to happen
before beginning to access SDRAM.
I2C EEPROMs
Most of the information needed to program the SDRAM speed attributes
and size is provided by EEPROM devices that are connected to Hawk’s
I2C bus. The EEPROM devices contain data in a specific format called
Serial Presence Detect (SPD).
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