Motorola MVME2400 Series Wartungshandbuch PDF herunterladen (Seite 231)

Programming Model

http://www.mcg.mot.com/literature 3-45

Note that RAM_E/F/G/H_BASE are located at

$FEF800C8 (refer to the section on SDRAM Base

Address Register (Blocks E/F/G/H). They operate the

same for blocks E-H as these bits do for blocks A-D.

Also note that the combination of RAM_X_BASE

and

ram_x_siz

should never be programmed such that

SDRAM responds at the same address as the CSR,

ROM/Flash, External Register Set, or any other slave on

the PowerPC bus.

CLK Frequency Register

CLK FREQUENCY

These bits should be programmed with the hexadecimal

value of the operating CLOCK frequency in MHz (i.e.

$42 for 66MHz). When these bits are programmed this

way, the chip’s prescale counter produces a 1MHz

(approximate) output. The output of the chip prescale

counter is used by the refresher/scrubber and the 32-bit

counter. After power-up, this register is initialized to $64

(for 100MHz). The formula is:

Counter_Output_Frequency = (Clock

Frequency)/CLK_FREQUENCY

For example, if the Clock Frequency is 100MHz and

CLK_FREQUENCY is $64, then the counter output

frequency is 100MHz/100 = 1MHz.

When the CLK pin is operating slower than 100MHz,

software should program CLK_FREQUENCY

to be at

least as slow as the CLK pin’s frequency as soon as

ADDRESS

$FEF80020

BIT

NAME

CLK FREQUENCY

por

OPERATIO

READ/WRITE READ ZERO READ ZERO

R/C

RESET

64 P X X

1 P

1 2 ... 226 227 228 229 230 231 232 233 234 235 236 ... 353 354

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