Motorola MVME2400 Series Wartungshandbuch PDF herunterladen (Seite 161)

Registers

http://www.mcg.mot.com/literature 2-103

GBL Global Enable. If set, the PPC master will assert the

GBL_ pin for each PPC transaction originated by the

corresponding PCI slave.

RAEN Read Ahead Enable. If set, read ahead is enabled for the

corresponding PCI slave.

WPEN Write Post Enable. If set, write posting is enabled for the

corresponding PCI slave.

WEN Write Enable. If set, the corresponding PCI slave is

enabled for write transactions.

REN Read Enable. If set, the corresponding PCI slave is

enabled for read transactions.

RMFTx Read Multiple FIFO Threshold. This field is used by

the PHB to determine a FIFO threshold at which to

continue prefetching data from local memory during PCI

read multiple transactions. This threshold applies to

subsequent prefetch reads since all initial prefetch reads

will be four cache lines. This field is only applicable if

read-ahead has been enabled. The encoding of this field is

shown in the table below.

The PCI Slave Offset Registers

(PSOFFx) contain offset information

associated with the mapping of PCI memory space to PPC memory space.

The field within the PSOFFx registers is defined as follows:

PSOFFx PCI Slave Offset. This register contains a 16-bit offset

that is added to the upper 16 bits of the PCI address to

determine the PPC address used for transfers from PCI to

the PPC bus. This offset allows PPC resources to reside at

addresses that would not normally be visible from PCI.

RMFT/RXFT Subsequent Prefetch FIFO Threshold

00 0 Cache lines

01 1 Cache line

10 2 Cache lines

11 3 Cache lines

1 2 ... 156 157 158 159 160 161 162 163 164 165 166 ... 353 354

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Motorola MVME2400 Series Wartungshandbuch Seite 161