Motorola MVME2400 Series Wartungshandbuch PDF herunterladen (Seite 140)

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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

field in the EATTR register. When the XDPEI bit in the

EENAB register is set, the assertion of this bit will assert

an interrupt through the MPIC.

PPER PCI Parity Error. This bit is set when the PCI PERR_

pin is asserted. It may be cleared by writing it to a 1;

writing it to a 0 has no effect. When the PPERM bit in the

EENAB register is set, the assertion of this bit will assert

MCHK to the master designated by the DFLT bit in the

EATTR register. When the PPERI bit in the EENAB

interrupt through the MPIC.

PSER PCI System Error. This bit is set when the PCI SERR_

pin is asserted. It may be cleared by writing it to a 1;

writing it to a 0 has no effect. When the PSERM bit in the

EENAB register is set, the assertion of this bit will assert

MCHK to the master designated by the DFLT bit in the

EATTR register. When the PSERI bit in the EENAB

interrupt through the MPIC.

PSMA PCI Master Signalled Master Abort. This bit is set

when the PCI master signals master abort to terminate a

PCI transaction. It may be cleared by writing it to a 1;

writing it to a 0 has no effect. When the PSMAM bit in the

EENAB register is set, the assertion of this bit will assert

MCHK to the master designated by the XID field in the

EATTR register. When the PSMAI bit in the EENAB

interrupt through the MPIC.

PRTA PCI Master Received Target Abort. This bit is set when

the PCI master receives target abort to terminate a PCI

transaction. It may be cleared by writing it to a 1; writing

it to a 0 has no effect. When the PRTAM bit in the

EENAB register is set, the assertion of this bit will assert

MCHK to the master designated by the XID field in the

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Motorola MVME2400 Series Wartungshandbuch Seite 140