Motorola M68000 Betriebsanweisung Seite 41
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Microcomputer Architecture 27
Answers
1. CPU, memory, and I/O.
2. The MC68000 transfers two bytes of data to and from memory, while
the MC68008 only transfers one byte.
3. The MC68030.
4. No.
5. 32 bits.
6. The MC68000 and the MC68010 are 16-bit buses, while the MC68020
and the MC68030 are 32-bit buses.
7. Asynchronous.
8. RAM can be read and written, while ROM can only be read.
9. Supervisor mode allows the design of operating systems that can make
it more difficult for a user s program to crash the system.
10. Much faster.
11. 16 megabytes.
12. D0-D7 and A0-A7.
13. The lowest.
14. No, an instruction can be one or more words. The first word is the
opcode word.
15. The PC contains the addresses of the instructions as they are executed.
16. A7.
17. None; memory-mapped I/O is used.
- ^UcMttaL P. SizUuijeS i 1
- A55EMBLY LANGUAGE 3
- PROGRAMMING TOR 3
- THE 68000 FAMILY 3
- ASSEMBLY LANGUAGE 5
- PROGRAMMING FOR 5
- TNE 68000 FAMILY 5
- To my wife Linda 7
- CONTENTS 11
- CHAPTER 8: Subroutines 99 12
- Contents xl 13
- INTRODUCTION 15
- Introduction 3 17
- NUMBER SYSTEMS 19
- Conversions 20
- Number Systems 7 21
- Hexadecimal 22
- 2. We can go from binary 23
- 2 is F0Ai6 23
- 2 gives us: 23
- Representing Negative Values 25
- ASCII Character Codes 26
- 21. binary 29
- CHAPTER 2 31
- ADDRESS MEMORY 35
- User and Supervisor Modes 37
- The CPU Registers 38
- User Programmer's Model 39
- Input/Output 40
- ASSEMBLER SOURCE FORMAT 43
- The Label Field 44
- The Operation Field 46
- The Operand Field 46
- The Comment Field 47
- On Choosing Symbols 48
- Constants 48
- $1100111001 11001110012 49
- Data-Defining Directives 50
- Symbol Equates 51
- The END Directive 52
- Assembler Source Format 39 53
- CHAPTER 4 55
- Data Movement 55
- Getting Started 43 57
- Addition and Subtraction 58
- Getting 5tarted 45 59
- Input and Output 61
- The Program Shell 63
- Getting Started 51 65
- Putting It All Together 67
- Getting 5tarted 55 69
- #'0',DO 70
- 19. SUB.L D1,D0 70
- CHAPTER 5 71
- CONDITION CODE REGISTER 72
- The Carry Bit 72
- 11101001 73
- + 10110111 73
- 110100000 73
- The Overflow Bit 75
- The Zero and negative Bits 75
- The Extend Bit 76
- Com parisons 76
- CHP.L DirDO 78
- BLE LABEL 78
- ADDQ and SUBQ Instructions 80
- MOVEQ #100,DO 81
- MOVE.L #100,DO 81
- BGE LABEL 84
- ADDRESSING MODES 85
- Register Direct Modes 86
- Im mediate Data 86
- Absolute Addressing 87
- Address Register Indirect 88
- Addressing Modes 75 89
- Addressing Modes 77 91
- Addressing Modes 79 93
- Addressing Modes 81 95
- Addressing Modes 83 97
- Addressing Mode Summary 98
- Addressing Modes 87 101
- CHAPTER 7 103
- Stack Instructions 103
- HIGH ADDRESS 104
- LOU ADDRESS 104
- The 5tach 91 105
- LOW ADDRESS 106
- Stack Applications 107
- The Stack 95 109
- Exercises 110
- PEA COUNT 111
- CHAPTER 8 113
- Subroutines 101 115
- Passing Param eters 116
- Subroutines 103 117
- ARG2: DS.L 118
- Subroutines 105 119
- Subroutines 107 121
- ADDA. L # 1 2 ,SP 122
- Stack Fram es 123
- ID BYTES OF LOCALS 124
- Subroutines 111 125
- Subroutines 113 127
- Subroutines 115 129
- CHAPTER 9 131
- * Q 139
- CHAPTER 10 143
- Logical Operations 144
- 01000100 145
- LSL'ASL 147
- Bit Manipulation 151
- BTSTr BSET, BCLR, BCBG 152
- Operand 1 153
- Operand 2 153
- CHAPTER 11 155
- Advanced Arithmetic 143 157
- Multiplication and Division 159
- 11100001 160
- Advanced Arithmetic 147 161
- Decimal Arithmetic 162
- Advanced Arithmetic 149 163
- Advanced Arithmetic 151 165
- 10000 0000 165
- Advanced Arithmetic 153 167
- EXCEPTION PROCESSING 169
- SYSTEM CONTROL 169
- OPERATIONS, AND I/O 169
- OVFLs DS.B 1 171
- OVERFLOW FLAG BYTE 171
- Exception Processing 172
- TRAP #<vector> 175
- ADD.L DO fDl 176
- CHK <ea>,Dn 176
- Serial I/O 177
- I I I I I I I I I I 178
- Miscellaneous Instructions 182
- 8. l e a u s t a c k ,a o 185
- C m P T f fl 15 187
- MOVE.L (AO)+,MEMLOC 188
- Virtual Machines 189
- Virtual Address Space 190
- Physical Memory 190
- Reference Classifications 191
- The Vector Base Register 192
- RTD and Loop Mode 193
- Summ ary 195
- 9. MOVE CCR,DO 196
- PC0, FC1, and FC2 196
- The 68010 183 197
- CHAPTER 1 4 199
- Instruction Caching 200
- The 68020 187 201
- Additional Addressing Modes 202
- The 68020 189 203
- MOVE.W #24,DO 203
- MOVE.L (0,A0,D0.W*4),D1 203
- Instruction Extensions 204
- The 68020 191 205
- Hew Instructions 207
- The 68020 195 209
- CAS Dc,Du,<ea> 210
- The 68020 197 211
- The 68020 201 215
- CHAPTER 15 217
- Instruction and Data C aches 218
- The 68030 205 219
- Pipelined Architecture 220
- Paged Memory Management 220
- requires 10 bits, leaving 221
- The 68030 209 223
- B-level tables 224
- "1 TT1 225
- 68030 Instructions 225
- The 68030 213 227
- ASCII CHARACTER CODES 229
- PROGRAM SHELLS AND 231
- I/O SUBROUTINES 231
- ! tSt.l dO 232
- Appendix B 219 233
- Appendix B 221 235
- ;plain style 236
- Appendix B 225 237
- ; return; 238
- Appendix B 227 241
- 68000-68020 243
- 0 S 0 S 244
- 0 S S 0 0 Test Operand 246
- 00000 Unlink 246
- 00000 UnPack BCD 246
- Appendix C 233 247
- 236 Index 250
- Index 237 251
- 238 Index 252
- Index 239 253
- ^ U a m a i P 256
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