Motorola MCU 68HC912D60 Bedienungsanleitung PDF herunterladen (Seite 2)

2 68HC912D60MSE4 Rev 2

March 14, 2001

ATD: CONVERSION OF THE (VRH-VRL)/2 INTERNAL REF VOLTAGE

RETURNS $7F, $80 OR $81 AR311

The (VRH-VRL)/2 internal reference conversion result may be $7F, $80 or $81.

Work-

around

If the (VRH-VRL)/2 internal reference is used (perhaps for system diagnostics),

expected pass result may be $7F, $80 or $81.

BDM: CLKSW IS CLEARED BY FIRMWARE AR461

This is primarily an issue only for developers of BDM interface equipment (BDM

pods). The BDM logic was changed to allow switching between XTAL/2 and a

possibly faster bus rate clock. If you set the CLKSW bit (faster bus rate clock) in

the BDM STATUS register (with a WRITE_BD_BYTE @ FF01 command, and then

later send a GO, TRACE1, or TAG_GO command (or encounter a $00 opcode with

ENBDM=0), the CLKSW bit is cleared by BDM firmware such that the BDM speed

switches back to the default (XTAL/2) rate.

Work-

around

When communicating at the bus rate (CLKSW=1), issue a new WRITE_BD_BYTE

command (at the XTAL/2 rate) to set the CLKSW bit in BDM_STATUS after any

GO, TRACE1, or TAG_GO command or if BDM communications fail unexpectedly.

BDM: FAILURE TO RELEASE ADDRESS BUS AFTER MEMORY ACCESSAR538

When the BDM module is using XTAL/2 as its reference clock and the PLL is

providing the clock for the CPU buses, a BDM logic circuit can fail to release control

of the address bus after completing a memory access. When the next BDM serial

command is completed, the BDM gives up control of the address bus, but by this

time the CPU is already lost. This often results in the CPU eventually reaching a

$00 opcode and getting into active BDM mode.

Work-

around

The error can be avoided if the BDM operates from the same clock source as the

bus. Everything works after reset because both the BDM and the bus use XTAL/2

as the clock source. If the CLKSW bit is changed to one before engaging the PLL,

the system also works (although the host must change communication speed to

match the bus frequency changes).

In some systems the PLL is turned on and off and the bus frequency can be

changed at random intervals and there is no practical way for a host to track these

changes without access to the E-clock frequency. In these systems there is no

workaround.

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Motorola MCU 68HC912D60 Bedienungsanleitung Seite 2