Motorola MPC5200 Bedienungsanleitung Seite 9

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Bright Star Engineering, Inc. Page 4
Table 1. Reset configuration register
Bit Pin Signal Value Description
0 Y18 ATA_DACK_L 0
1 Y17 ATA_IOR_L 0
2 W17 ATA_IOW_L 0
3 W16 LP_R_W_L 1
4 V14 LP_ALE_L 0
Core PLL configuration [4:0]
XLB:CORE:FVCO = 1:3:6
5 Y13 LP_TS_L 0 XLB_CLK = SYS_PLL_FVCO/4
6 H2 USB_1_USB1_TX_N 0 SYS_PLL_FVCO = SYS_PLL_FREFx16
7 H3 USB_2_USB1_TX_P 0 FVCO = 12x or 16x SYS_XTAL
8 K1 E0_MII_TX_EN 0 Most Graphics boot disabled
9
1
K2 E1_MII_TXD0 0 Large Flash boot disabled
10 K3 E2_MII_TXD1 1 Boot address: 0xFFF0 0100
11 J1 E3_MII_TXD2 1 48 IPbus clocks of waitsate
12 J2 E4_MII_TXD3 0 Same endian ROM
13 L3 E5_MII_TX_ERR 0 8 bit data, 24 bit address ROM
14 N2 E6_MII_MDC 0 Non-mux-ed boot ROM
1
MPC5200 documentation sometimes calls this bit 15 with the same functionality
2.4 Clocks
Onboard clocks consist of the system clock (33.000 MHz, ±50 Hz/MHz), the RTC clock
(32.768 kHz, ±20 Hz/MHz)*, and the Ethernet clock (25.000 MHz, ±50 Hz/MHz).
The MPC5200 drives the PCI_CLK signal (33.000 MHz).
Table 2. MPC5200 Clock frequencies
Clock Frequency/MHz Comments
SYS_XTAL_IN 33.000
f
VCOsys
528.00
f
SYSTEM
528.00
Reset Configuration bits [6:7] = 00
f
VCOcore
792.00
603e Core 398.00
Reset Configuration bits [0:4] = 00010
XLB_CLK 132.00 Reset Configuration bits [5] = 0
MEM_CLK 132.00 Same as XLB_CLK
IPB_CLK 66.000 Default. May be configured as 132 MHz
2
PCI_CLK 33.000 Must be configured as 33 MHz
2
USB_CLOCK 48.000 Divide by 11
2
DCM Config Reg = 0x0011 (default) or 0x0013 for 132 MHz IPB_CLK
* Note: The RTC feature has no onboard battery. The PowerEngine must remain powered
for RTC functionality. Alternatively, an external RTC may be used.
2.5 Interrupts
Three of the four dedicated interrupts are available to the user. If PCI is used, IRQ0 must
be used. IRQ2 is dedicated to the onboard Ethernet PHY. In addition to these interrupts,
several programmable pins (GPIO_INT) may be configured as interrupts.
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