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Bright Star Engineering, Inc. Page 11

Table 12. Ethernet port description

MPC5200 Port Mode

Port Pin Reset Cfg. ETH18/MD ETH7 ETH7/J1850

J1 Pin Comments

ETH_0 K1 RST_CFG_8 TXEN TXEN TXEN n/a

ETH_1 K2 RST_CFG_9 TXD_0 TXD TXD n/a

ETH_2 K3 RST_CFG_10 TXD_1 GPO GPO n/a

ETH_3 J1 RST_CFG_11 TXD_2 GPO GPO n/a

ETH_4 J2 RST_CFG_12 TXD_3 GPO J1850_TX 156 via MUX, ETH7 mode

ETH_5 L3 RST_CFG_13 TXERR GPO GPO n/a

ETH_6 N2 RST_CFG_14 MDC GPO GPO n/a

ETH_7 N1 RST_CFG_15 MDIO GPO GPO n/a

ETH_8 M3 RXDV CD CD n/a

ETH_9 L1 RXCLK RXCLK RXCLK n/a

ETH_10 J3 COL COL COL n/a

ETH_11 L4 TXCLK TXCLK TXCLK n/a

ETH_12 M2 RXD_0 RXD RXD n/a

ETH_13 M1 RXD_1 GPIO_INT J1850_RX 159 via MUX, ETH7 mode

ETH_14 N4 RXD_2 GPIO_INT GPIO_INT n/a

ETH_15 N3 RXD_3 GPIO_INT GPIO_INT n/a

ETH_16 L2 RXERR GPIO_INT GPIO_INT 165 via MUX, ETH7 mode

ETH_17 J4 CRS GPIO_WKUP GPIO_WKUP 160 via MUX, ETH7 mode

3.10 Ethernet

The MPC5200 Ethernet port may be configured in ETH18 w/ MD (MII mode,

10/100BASE-T), ETH7 or ETH7 w/ J1850 (7-wire/GPSI, 10BASE-T only) modes only.

The AMD AM79C874 chip is used for the Ethernet PHY along with the internal

controller. Magnetics must be provided on the main board. The Ethernet Receive and

Transmit differential pairs are routed with an intrinsic impedance (Z

) of 100 Ω. The

Ethernet PHYAD is hard-wired to 0x01.

The Ethernet PHY may be configured in MII mode which allows 100BASE-T as well as

10BASE-T or in 7-wire (GPSI) mode which allows 10BASE-T only. Due to the

MPC5200 multiplexing of the J1850 and MII signals, 7-wire mode must be used when

J1850 is functioning, thus, restricting Ethernet communication to 10 Mbit/s. The mode of

operation is selected by the PHY chip when it comes out of reset. In order to change the

mode on-the-fly, Two pins on the MPC5200 USB port are used: ENET_RST_L (USB_9,

pin F3) and SEL_E10_L (USB_0, pin H1).

Both signals are active low. The PHY chip can be set to the desired mode by asserting

ENET_RST_L, setting SEL_E10_L to the proper polarity (0 for 10BASE-T, 1 for

100BASE-T), then de-asserting the reset bit.

When in 7-wire mode, ETH_4 (pin, J2) and ETH_13 (pin, M1) are switched to the

connector for J1850 transmit and receive signals respectively. As an alternative, ETH_4

can be a general purpose output and ETH_13 can be a GPIO_INT. In addition to these

two signals, ETH_16 (pin L2) and ETH_17 (pin J2) are also switched to the connector as

GPIO_INT and GPIO_WKUP respectively.

Two LED control signals are available; one for link and one for activity. Both signals are

active low. A forward current of 10 mA is recommended. LEDs should be biased to 3.3

Note: The LINK_LED_L signal is active low in both MII and 7-wire modes.

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