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SPRS292 − OCTOBER 2005

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

HOST-PORT INTERFACE TIMING (CONTINUED)

1st halfword 2nd halfword

HAS

HCNTL[1:0]

HR/W

HHWIL

HSTROBE

†

HCS

HD[15:0] (input)

HRDY

†

HSTROBE

refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 44. HPI Write Timing (HAS Not Used, Tied High)

1st half-word 2nd half-word

HAS

†

HCNTL[1:0]

HR/W

HHWIL

HSTROBE

‡

HCS

HD[15:0] (input)

HRDY

†

For correct operation, strobe the HAS

signal only once per HSTROBE active cycle.

‡

HSTROBE

refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 45. HPI Write Timing (HAS Used)

1 2 ... 85 86 87 88 89 90 91 92 93 94 95 ... 106 107

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Motorola TMS320C6711D Bedienungsanleitung Seite 90