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3
Note: The information in Table 3-12 is appropriate when configured with
devices with an access time equal to 5 CLK periods.
Note: The information in Table 3-13 is appropriate when configured with
devices with an access time equal to 3 CLK periods.
Table 3-12. PPC Bus to ROM/Flash Access Timing (50ns @ 100MHz)
ACCESS TYPE
CLOCK PERIODS REQUIRED FOR:
Total
Clocks
1st Beat 2nd Beat 3rd Beat 4th Beat
16
Bits
64
Bits
16
Bits
64
Bits
16
Bits
64
Bits
16
Bits
64
Bits
16
Bits
64
Bits
4-Beat Read 42 15 36 9 36 9 36 9 150 42
4-Beat Write N/A N/A
1-Beat Read (1 byte) 1515------1515
1-Beat Read (2 to 8 bytes)4215------4215
1-Beat Write 2121------2121
Table 3-13. PPC Bus to ROM/Flash Access Timing (30ns @ 100MHz)
ACCESS TYPE
CLOCK PERIODS REQUIRED FOR:
Total
Clocks
1st Beat 2nd Beat 3rd Beat 4th Beat
16
Bits
64
Bits
16
Bits
64
Bits
16
Bits
64
Bits
16
Bits
64
Bits
16
Bits
64
Bits
4-Beat Read 34 13 28 7 28 7 28 7 118 34
4-Beat Write N/A N/A
1-Beat Read (1 byte) 1313------1313
1-Beat Read (2 to 8 bytes)3413------3413
1-Beat Write 2121------2121
- MVME2400-Series 1
- Single Board Computer 1
- Installation and Use 1
- Restricted Rights Legend 2
- Document Terminology 4
- Safety Summary 5
- Safety Depends On You 5
- Contents 9
- Glossary 12
- List of Figures 13
- List of Tables 15
- 1Preparing and Installing the 17
- MVME2400-Series Module 17
- MVME240x Module 18
- PMCspan Expansion Mezzanine 19
- PCI Mezzanine Cards (PMCs) 19
- VMEsystem Enclosure 20
- System Console Terminal 20
- 1 2 3 4 5 6 7 8 25
- ESD Precautions 29
- 2064 9708 31
- Primary PMCspan 32
- 2081 9708 33
- Secondary PMCspan 34
- 2065 9708 35
- INTERRUPT ACKNOWLEDGE 38
- DEBUG port on 38
- Installation Considerations 39
- 2Operating Instructions 41
- Switches 42
- MVME240x 43
- Status Indicators 44
- 10/100 BASET Port 44
- DEBUG Port 45
- Operating Instructions 46
- PMC Slots 47
- 3Functional Description 49
- (RST) and Abort (ABT) 50
- General Description 52
- Block Diagram 52
- (PHB) ASIC 55
- PCI Bus Latency 56
- 3:1 clock ratio: 56
- PPC Bus Latency 58
- Assumptions 60
- SDRAM Memory 62
- Functional Description 66
- Flash Memory 67
- Ethernet Interface 70
- VMEbus Interface 73
- Asynchronous Debug Port 73
- PCI Host Bridge (PHB) 75
- Interrupt Controller (MPIC) 76
- Programmable Timers 76
- 4Programming the MVME240x 79
- Processor Bus Memory Map 80
- PCI Local Bus Memory Map 81
- VMEbus Memory Map 81
- Programming Considerations 82
- Interrupt Handling 84
- DMA Channels 86
- Sources of Reset 86
- Endian Issues 88
- Programming the MVME240x 90
- PPCBug Overview 91
- PPCBug Basics 91
- Diag> 92
- Memory Requirements 93
- PPCBug Implementation 93
- Debugger Commands 96
- Table 5-1. Debugger Commands 97
- Diagnostic Tests 100
- Using PPCBug 101
- 6Modifying the Environment 103
- Modifying the Environment 104
- ENV - Set Environment 105
- ∗ signal after 107
- ∗ signal during board 107
- 00001000? 111
- (Default) 112
- Ordering Related 119
- Documentation 119
- Manufacturers’ Documents 120
- Document Title and Source 121
- Publication 121
- Related Specifications 123
- Specifications 127
- Table B-1. MVME240 128
- Specifications (Continued) 128
- Cooling Requirements 129
- EMC Regulatory Compliance 130
- CConnector Pin Assignments 131
- VMEbus Connector - P1 132
- Connector Pin Assignments 133
- VMEbus Connector - P2 134
- Pin Assignments 136
- CPU Debug Connector - J1 137
- PCI Expansion Connector - J6 142
- DTroubleshooting the MVME240x 151
- Solving Startup Problems 152
- Troubleshooting the MVME240x 153
- Numerics 169
- Single Board Computer 177
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