Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66C)
155
7.4.11 NAND Flash Chip 1 Presence Register
CE2 Chip Enable 2
1 CE2 is asserted when the device is accessed.
0 CE2 is not asserted when the device is accessed.
CE3 Chip Enable 3
1 CE3 is asserted when the device is accessed.
0 CE3 is not asserted when the device is accessed.
CE4 Chip Enable 1
1 CE4 is asserted when the device is accessed.
0 CE4 is not asserted when the device is accessed.
RSVD Reserved
Table 7-24 NAND Flash Chip 1 Select Register Field Definition
Table 7-25 NAND Flash Chip 1 Presence Register, 0xF200_0012
Bit Field Operation Reset
7C1PR X
6RSVDR 0
5RSVDR 0
4RSVDR 0
3RSVDR 0
2RSVDR 0
1RSVDR 0
0RSVDR 0
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