Motorola CPU32 Bedienungsanleitung PDF herunterladen (Seite 14)

100

101

Introduction

MOTOROLA

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

1-3

1.1.3 Program Counter

The PC contains the address of the instruction currently executing. During instruction

execution and exception processing, the processor automatically increments the contents

or places a new value in the PC. For some addressing modes, the PC can be used as a

pointer for PC relative addressing.

1.1.4 Condition Code Register

Consisting of ﬁve bits, the CCR, the status register’s lower byte, is the only portion of the

status register (SR) available in the user mode. Many integer instructions affect the CCR,

indicating the instruction’s result. Program and system control instructions also use certain

combinations of these bits to control program and system ﬂow. The condition codes meet

two criteria: consistency across instructions, uses, and instances and meaningful results

with no change unless it provides useful information.

Consistency across instructions means that all instructions that are special cases of more

general instructions affect the condition codes in the same way. Consistency across uses

means that conditional instructions test the condition codes similarly and provide the same

results whether a compare, test, or move instruction sets the condition codes. Consistency

across instances means that all instances of an instruction affect the condition codes in the

same way.

The ﬁrst four bits represent a condition of the result generated by an operation. The ﬁfth bit

or the extend bit (X-bit) is an operand for multiprecision computations. The carry bit (C-bit)

and the X-bit are separate in the M68000 family to simplify programming techniques that use

them (refer to Table 3-18 as an example). In the instruction set deﬁnitions, the CCR is

illustrated as follows:

X—Extend

Set to the value of the C-bit for arithmetic operations; otherwise not affected or set to a

speciﬁed result.

N—Negative

Set if the most signiﬁcant bit of the result is set; otherwise clear.

Z—Zero

Set if the result equals zero; otherwise clear.

V—Overﬂow

Set if an arithmetic overﬂow occurs implying that the result cannot be represented in the

operand size; otherwise clear.

XNZVC

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