Motorola MVME712AM Bedienungsanleitung PDF herunterladen (Seite 2)

F e a t u r e s

• 25 or 33 MHz MC68040 32-bit microprocessor with 8KB

of cache, MMU, and FPU

• Full 32-bit master/slave VMEbus interface

• High performance DMA supports VMEbus D64 and local

bus memory burst cycles

• 4, 8, 16, 32 or 64MB on-board DRAM, four-way

interleaved, with programmable parity checking or Error

Checking and Correction (ECC) option

• On-board SCSI interface with 32-bit local bus burst DMA

• On-board Ethernet interface with 32-bit local bus DMA

• Four 44-pin sockets for up to 4MB on-board

ROM/EPROM

• Four EIA-232-D serial ports implemented with quad serial

I/O processor

• 8-bit, bidirectional, Centronics

compatible parallel port

• Four 32-bit timers and one watchdog timer

• 8KB of NVRAM with real-time clock/calendar

• Remote Reset/Abort/Status control functions

• Completely programmable for maximum integration

flexibility

• Low power consumption—less than 20 watts typical

• 27.7 MIPS @ 25 MHz

• 36.8 MIPS @ 33 MHz

O r d e r i n g I n f o r m a t i o n

Part Number Description

MVME167-001y 25 MHz, 4MB DRAM, parity

MVME167-002y 25 MHz, 8MB DRAM, parity

MVME167-003y 25 MHz, 16MB DRAM, parity

MVME167-004y 25 MHz, 32MB DRAM, parity

MVME167-031y 33 MHz, 4MB ECC DRAM

MVME167-032y 33 MHz, 8MB ECC DRAM

MVME167-033y 33 MHz, 16MB ECC DRAM

MVME167-034y 33 MHz, 32MB ECC DRAM

Note: y indicates product revision level if any; for example, “-001A.”

Related Documentation

68-MVME167SET Manual Set for use with the MVME167

68-1X7DS Includes user’s manuals for each of the peripheral

controllers used on the MVME167 Series

MVME167 Memory Map

Address Range Devices Accessed Port Size Size

Software

Cache

Inhibit

Notes

$00000000–DRAMsize User Programmable

(On-Board DRAM)

D32 DRAMsize No 1, 2

DRAMsize–$FF7FFFFF User Programmable

(VMEbus)

D32/D16 3GB No 3, 4

$FF800000–$FFBFFFFF ROM D32 4MB No 1

$FFC00000–$FFDFFFFF Reserved — 2MB — 5

$FFE00000–$FFE1FFFF SRAM D32 128KB No —

$FFE20000–$FFEFFFFF SRAM (repeated) D32 896KB No —

$FFF00000–$FFFEFFFF Local I/O Devices D8-D32 1MB Yes 3

$FFFF0000–$FFFFFFFF User Programmable

(VMEbus A16)

D32/D16 64KB No 2, 4

Notes:

1. On-board EPROM appears at $00000000–$003FFFFF following a local bus reset. The EPROM

appears at 0 until the ROM0 bit is cleared in the VMEchip2. The ROM0 bit is located at address

$FFF40030 bit 20. The EPROM must be disabled at 0 before the DRAM is enabled. The VMEchip2

and DRAM map decoders are disabled by a local bus reset.

2. This area is user-programmable. The suggested use is shown in the table. The DRAM decoder is

programmed in the MEM040 or MCECC chip, and the local-to-VMEbus decoders are programmed

in the VMEchip2.

3. Size is approximate.

4. Cache inhibit depends on devices in area mapped.

5. This area is not decoded. If these locations are accessed and the local bus timer is enabled, the cycle

times out and is terminated by a TEA signal.

1 2 3 4

Kommentare zu diesen Handbüchern

Keine Kommentare

Motorola MVME712AM Bedienungsanleitung Seite 2

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Nein Motorola MVME712AM