Motorola M68CPU32BUG Bedienungsanleitung Seite 46
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DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-60
T Trace T
3.30 TRACE
T [<count>]
Use the T command to execute one instruction at a time and display the target state after
execution. T starts tracing at the address in the target PC. The optional count field specifies the
number of instructions to be traced before returning control to CPU32Bug. The count field
default is 1. As each instruction is traced, a register display printout is generated.
During tracing, breakpoints in ROM or write protected memory are monitored (but not inserted)
for all trace commands which allow the use of breakpoints in ROM or write protected memory.
Control is returned to CPU32Bug if a breakpoint with 0 count is encountered.
Trace functions are implemented with the trace bits (T0, T1) in the MCU device status register.
Do not modify trace bits (T0, T1) while using the trace commands. Because the trace functions
are implemented using the hardware trace bits in the MCU, code in ROM can be traced. During
trace mode, breakpoints are monitored and their counts decremented when the corresponding
instruction with breakpoint is traced. This allows breakpoints to work in ROM, but only in the
trace mode.
EXAMPLE The following program resides at location $7000.
CPU32Bug>MD 7000;DI<CR>
00007000 2200 MOVE.L D0,D1
00007002 4282 CLR.L D2
00007004 D401 ADD.B D1,D2
00007006 E289 LSR.L #$1,D1
00007008 66FA BNE.B $7004
0000700A E20A LSR.B #$1,D2
0000700C 55C2 SCS.B D2
0000700E 60FE BRA.B $700E
CPU32Bug>
Initialize PC and D0:
CPU32Bug>RM PC<CR>
PC =00008000 ? 7000.<CR>
CPU32Bug>RM D0 <CR>
D0 =00000000 ? 8F4IC.<CR>
DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-61
T Trace T
Display target registers and trace one instruction:
CPU32Bug>RD<CR>
PC =00007000 SR =2700=TR:OFF_S_7_..... VBR =00000000
SFC =0=F0 DFC =0=F0 USP =0000382C SSP* =00004000
D0 =0008F41C D1 =00000000 D2 =002003A2 D3 =00000000
D4 =00000000 D5 =00000000 D6 =00000000 D7 =00000000
A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000
A4 =00000000 A5 =00000000 A6 =00000000 A7 =00004000
00007000 2200 MOVE.L D0,D1
CPU32Bug>T<CR>
PC =00007002 SR =2700=TR:OFF_S_7_..... VBR =00000000
SFC =0=F0 DFC =0=F0 USP =0000382C SSP* =00004000
D0 =0008F41C D1 =0008F41C D2 =002003A2 D3 =00000000
D4 =00000000 D5 =00000000 D6 =00000000 D7 =00000000
A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000
A4 =00000000 A5 =00000000 A6 =00000000 A7 =00004000
00007002 4282 CLR.L D2
CPU32Bug>
Trace next instruction:
CPU32Bug><CR>
PC =00007004 SR =2704=TR:OFF_S_7_..Z.. VBR =00000000
SFC =0=F0 DFC =0=F0 USP =0000382C SSP* =00004000
D0 =0008F41C D1 =0008F41C D2 =00000000 D3 =00000000
D4 =00000000 D5 =00000000 D6 =00000000 D7 =00000000
A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000
A4 =00000000 A5 =00000000 A6 =00000000 A7 =00004000
00007004 D401 ADD.B D1,D2
CPU32Bug>
Fr
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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- M68CPU32BUG DEBUG MONITOR 1
- USER’S MANUAL 1
- M68CPU32BUG/D 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 3
- LIST OF TABLES 3
- 1.5 SYSTEM RESTART 5
- CHAPTER 1 5
- GENERAL INFORMATION 5
- 1.1 INTRODUCTION 5
- 1.2 GENERAL DESCRIPTION 5
- 1.3 USING THIS MANUAL 6
- 1.6 MEMORY REQUIREMENTS 7
- CHAPTER 2 9
- DEBUG MONITOR DESCRIPTION 9
- 2.1 INTRODUCTION 9
- Freescale Semiconductor, Inc 10
- 2.6 FUNCTION CODE SUPPORT 13
- CHAPTER 3 16
- DEBUG MONITOR COMMANDS 16
- 3.1 INTRODUCTION 16
- BC Block of Memory Compare BC 17
- BF Block of Memory Fill BF 17
- BS Block of Memory Search BS 19
- BM Block of Memory Move BM 19
- BR Breakpoint Insert BR 20
- BV Block of Memory Verify BV 21
- DU Dump S-Records DU 23
- DC Data Conversion DC 23
- GN Go To Next Instruction GN 25
- GO Go Execute User Program GO 27
- HE Help HE 29
- MA Macro Define/Display MA 31
- MAE Macro Edit MAE 33
- MM Memory Modify MM 35
- MD Memory Display MD 36
- MS Memory Set MS 38
- PF Port Format PF 39
- PA Printer Attached PA 40
- RD Register Display RD 41
- RS Register Set RS 43
- RESET Cold/Warm Reset RESET 44
- RM Register Modify RM 44
- T Trace T 45
- SD Switch Directories SD 45
- TM Transparent Mode TM 48
- 4.2SOURCE PROGRAM CODING 51
- CHAPTER 4 52
- ASSEMBLER/DISASSEMBLER 52
- 4.1 INTRODUCTION 52
- 5.2 SYSTEM CALL ROUTINES 57
- CHAPTER 5 58
- SYSTEM CALLS 58
- 5.1 INTRODUCTION 58
- .ERASLN Erase Line .ERASLN 61
- .OUTSTR .OUTSTR 66
- .SNDBRK Send Break .SNDBRK 68
- .TM_RD Read Timer .TM_RD 70
- .WRITELN .WRITELN 71
- .WRITDLN .WRITDLN 71
- 6.3 UTILITIES 73
- CHAPTER 6 73
- DIAGNOSTIC FIRMWARE GUIDE 73
- 6.1 INTRODUCTION 73
- 6.2 DIAGNOSTIC MONITOR 73
- CPU B Instruction Test CPU B 75
- CPU CPU Tests For The MCU CPU 76
- CPU A Register Test CPU A 76
- CPU C Address Mode Test CPU C 77
- MT Memory Tests MT 78
- MT D Set Bus Data Width MT D 79
- MT A Set Function Code MT A 79
- MT B Set Start Address MT B 80
- MT C Set Stop Address MT C 80
- MT H Random Byte Test MT H 81
- MT E March Address Test MT E 81
- MT F Walk a Bit Test MT F 82
- MT G Refresh Test MT G 82
- MT I Program Test MT I 83
- MT J Test and Set Test MT J 84
- BERR Bus Error Test BERR 84
- APPENDIX A 85
- S-RECORD INFORMATION 85
- A.1 INTRODUCTION 85
- A.2 S-RECORD CONTENT 85
- A.3 S-RECORD TYPES 86
- A.4 S-RECORDS CREATION 86
- C.2 CPU32BUG CUSTOMIZATION 87
- APPENDIX B 87
- SELF-TEST ERROR MESSAGES 87
- B.1 INTRODUCTION 87
- APPENDIX C 88
- USER CUSTOMIZATION 88
- C.1 INTRODUCTION 88
- C.3 CUSTOMIZATION TABLE 90
- C.4 COMMUNICATION FORMATS 93
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