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Boundary Scan JTAG Header Controls, LEDs, and Connectors
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
63
3.5.10 Boundary Scan JTAG Header
This 2x7 0.1" header is used to provide boundary scan testing of all onboard JTAG devices in
a single scan chain. The pin assignments for this header are as follows:
J16 pin 12 is grounded in the JTAG test cable. When the cable is attached, the CPU_BSCAN_L
signal is grounded, which automatically configures the boundary scan chain to include the CPU.
3.5.11 Processor JTAG/COP Header
The processor has a 2x8 0.1" JTAG/COP header for use with third party MPC745x JTAG/COP
controllers. The pin assignments for this header are as follows:
With no JTAG cable attached to J16, the CPU JTAG signals are routed to J17 as shown.
51 PMCIO51 PMCIO52 52
53 PMCIO53 PMCIO54 54
55 PMCIO55 PMCIO56 56
57 PMCIO57 PMCIO58 58
59 PMCIO59 PMCIO60 60
61 PMCIO61 PMCIO62 62
63 PMCIO63 PMCIO64 64
Table 3-11 PMC Connector Pin Assignments , J14/J24 (continued)
Pin J14/J24 Pin
Table 3-12 Boundary Scan JTAG Header Pin Assignments, J16
Pin Signal Pin
1TRST_L GND 2
3TDO GND 4
5TDI GND 6
7TMS GND 8
9TCK GND 10
11 NC CPU_BSCAN_L 12
13 AUTOWR_L GND 14
Table 3-13 Processor JTAG/COP Header Pin Assignments, J17
Pin Signal Pin Signal
1CPUTDO2QACK_L
3 CPUTDI 4 CPUTRST_L
5QREQ_L6+1.8 V
7 CPUTCK 8 CHKSTPI_L
- CPCI-6115 CompactPCI 1
- Single Board Computer 1
- Trademarks 2
- Contents 3
- List of Tables 10
- List of Figures 11
- About this Manual 13
- Abbreviations 14
- Conventions 16
- Summary of Changes 17
- Comments and Suggestions 18
- Safety Notes 19
- Operation 20
- Installation 20
- Cabling and Connectors 21
- Environment 22
- Sicherheitshinweise 23
- Schaltereinstellungen/Jumper 24
- Kabel und Stecker 26
- Umweltschutz 26
- Batterie 26
- Introduction 27
- 1.2 Standard Compliances 28
- 1.3 Ordering Information 29
- 2.1 Overview 31
- Requirements 32
- 2.3.2 Power Requirements 34
- 2.3.3 Thermal Requirements 34
- 2.4 Getting Started 37
- 2.5 Baseboard Preparation 38
- 2.5.3 J6, Bus Mode Selection 40
- 2.5.7 J20, Safe Start Header 42
- 2.6 Operating Modes 44
- 2.7 Installing Hardware 44
- Procedure 45
- Personal Injury or Death 46
- 2.9 Applying Power 49
- 3.1 Overview 51
- 3.2 Board Layout 52
- 3.4 ABORT/Reset Switch 54
- 3.5.7 CompactPCI Connector 58
- PCI_RSVD = PCI Reserved pin 62
- 3.5.14 Safe Start Header 67
- 3.5.15 Bus Mode Select Header 67
- 3.5.18 +/-12 V Present Header 68
- Functional Description 69
- 4.2 Block Diagram 70
- 4.3 General Description 71
- 4.3.2 Processor 72
- 4.3.3 L3 Cache 72
- 4.3.4.12 Interrupt Controller 76
- 4.3.4.13 PCI Bus Arbitration 76
- 4.3.4.14 Board Reset Logic 77
- 4.3.5 System Memory 81
- 4.3.6 Flash Memory 82
- 4.3.8 TL16C550C UART Devices 83
- 4.3.9 System Registers 83
- 4.3.10 Serial EEPROM Devices 83
- 4.3.11 PCI Bus 0.0 83
- 4.3.12 PCI Bus 1.0 83
- 4.3.13 IDE Controller 84
- 4.3.15 CompactPCI Bus 84
- 4.3.16 PMC Slots 84
- 4.4 Miscellaneous 86
- 4.4.3 Onboard Power Supplies 89
- 4.4.4 Hot Swap Support 89
- 4.4.5 Hot Swap Process 89
- 5.2 Block Diagram 92
- 5.4 Rear Panel Connectors 94
- 5.5.2.1 Host IO Connectors 96
- 5.5.2.2 PMC I/O Connectors 98
- 5.6 Jumper Settings 104
- 5.7 Functional Description 105
- 5.7.3 Hot-Swap Support 106
- 5.7.4 Serial EEPROM 106
- 5.7.5 PMC I/O Modules 106
- 5.7.7 PMC I/O Module 110
- 5.7.9 PMC I/O Connector 112
- 5.7.10 Host I/O Connector 112
- 5.8 Installing the PIM 113
- Figure 5-9 Installing the PIM 114
- Remote Start via the PCI Bus 117
- MOTLoad Firmware 119
- 7.4 MOTLoad Commands 120
- 7.6 MOTLoad Tests 120
- 7.7 Using MOTLoad 121
- 7.7.2 Command Line Help 122
- 7.7.3 Command Line Rules 122
- 7.8 MOTLoad Command List 123
- Memory Maps 127
- 8.2.2 Processor Memory Map 128
- 8.2.3 Default PCI Memory Map 129
- 8.2.5 System I/O Memory Map 131
- 8.2.7 CompactPCI Memory Map 131
- 8.2.9 L1, L2 and L3 Cache 132
- 8.2.10 System Memory 132
- A Related Documentation 133
- A.3 Related Specifications 134
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