Motorola MVME1X7P Bedienungsanleitung

MVME1X7P Single-Board ComputerProgrammer’s ReferenceGuideV1X7PA/PG1Edition of October 2000

xVMEbus Slave Address Modifier Select Register 1...2-36Programming the Local-Bus-to-VMEbus Map Decoders...

2-10 Computer Group Literature Center Web SiteVMEchip22Each map decoder includes an alternate address register and an alternate address select registe

Functional Blockshttp://www.motorola.com/computer/literature 2-112Using control register bits in the LCSR, the DMAC can be configured to provide the f

2-12 Computer Group Literature Center Web SiteVMEchip22The DMAC also supports command chaining through the use of a singly- linked list built in local

Functional Blockshttp://www.motorola.com/computer/literature 2-132and to allow transfers which are not an even byte count or which start at an odd add

2-14 Computer Group Literature Center Web SiteVMEchip22The DMAC requester requests the bus as required to transfer data to or from the FIFO buffer. Th

Functional Blockshttp://www.motorola.com/computer/literature 2-152Tick TimersThe VMEchip2 includes two general-purpose tick timers. These timers can b

2-16 Computer Group Literature Center Web SiteVMEchip22VMEbus InterrupterThe interrupter provides all the signals necessary to allow software to reque

Functional Blockshttp://www.motorola.com/computer/literature 2-172VMEbus System ControllerWith the exception of the optional SERCLK driver and the Pow

2-18 Computer Group Literature Center Web SiteVMEchip22In addition to the VMEbus timer, the chip contains a local bus timer. This timer asserts the lo

Functional Blockshttp://www.motorola.com/computer/literature 2-192Each of the 31 interrupts can be enabled to generate a local bus interrupt at any le

xiVME Access, Local Bus, and Watchdog Time-out Control Register ...2-66Prescaler Control Register ...

2-20 Computer Group Literature Center Web SiteVMEchip22The interrupt handler provides all logic necessary to identify and handle all local interrupts

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-2124. The operations possible on the register bits, defined as follows: 5. The sta

2-22 Computer Group Literature Center Web SiteVMEchip22Table 2-2. VMEchip2 Memory Map—LCSR Summary (Sheet 1 of 2)DMA TBSNP MODEROMZEROSRAMSPEEDADDER2

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-232ARBROBNMASTDHBMASTDWBMSTFAIRMSTRWDMASTERVMEBUSDMAHALTDMAENDMATBLDMAFAIRDMRELMDM

2-24 Computer Group Literature Center Web SiteVMEchip22Table 2-2. VMEchip2 Memory Map—LCSR Summary (Sheet 2 of 2)ENIRQ31ENIRQ30ENIRQ29ENIRQ28ENIRQ27E

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-252This sheet begins on facing page.0123456789101112131415VMEACCESSTIMERLOCALBUSTI

2-26 Computer Group Literature Center Web SiteVMEchip22Programming the VMEbus Slave Map DecodersThis section includes programming information for the

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-272You program a VMEbus slave map decoder by loading the starting address of the s

2-28 Computer Group Literature Center Web SiteVMEchip22$FFF40010. The adders allow any size board to be mapped on any 64KB boundary. The adders are di

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-292VMEbus Slave Ending Address Register 2 This register is the ending address regi

xiiI/O Control Register 2 ...2-97I/O Control Register 3 ...

2-30 Computer Group Literature Center Web SiteVMEchip22VMEbus Slave Address Translation Select Register 1 This register is the address translation sel

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-312VMEbus Slave Address Translation Address Offset Register 2This register is the

2-32 Computer Group Literature Center Web SiteVMEchip22VMEbus Slave Write Post and Snoop Control Register 2This register is the slave write post and s

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-332VMEbus Slave Address Modifier Select Register 2This register is the address mod

2-34 Computer Group Literature Center Web SiteVMEchip22A32 When this bit is high, the second map decoder responds to VMEbus A32 (extended) access cycl

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-352VMEbus Slave Write Post and Snoop Control Register 1This register is the slave

2-36 Computer Group Literature Center Web SiteVMEchip22VMEbus Slave Address Modifier Select Register 1This register is the address modifier select reg

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-372A32 When this bit is high, the first map decoder responds to VMEbus A32 (extend

2-38 Computer Group Literature Center Web SiteVMEchip22Each of the four programmable local bus map decoders has a starting address, an ending address,

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-392Write posting is enabled for the segment by setting the write post enable bit i

xiiiProgramming the Tick Timers ...3-18Tick Timer 1 Compare Register ...

2-40 Computer Group Literature Center Web SiteVMEchip22Local Bus Slave (VMEbus Master) Starting Address Register 1This register is the starting addres

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-412Local Bus Slave (VMEbus Master) Ending Address Register 3 This register is the

2-42 Computer Group Literature Center Web SiteVMEchip22Local Bus Slave (VMEbus Master) Starting Address Register 4 This register is the starting addre

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-432Local Bus Slave (VMEbus Master) Attribute Register 4 This register is the attri

2-44 Computer Group Literature Center Web SiteVMEchip22Local Bus Slave (VMEbus Master) Attribute Register 3 This register is the attribute register fo

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-452Local Bus Slave (VMEbus Master) Attribute Register 2 This register is the attri

2-46 Computer Group Literature Center Web SiteVMEchip22Local Bus Slave (VMEbus Master) Attribute Register 1 This register is the attribute register fo

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-472VMEbus Slave GCSR Group Address Register This register defines the group addres

2-48 Computer Group Literature Center Web SiteVMEchip22VMEbus Slave GCSR Board Address Register This register defines the board address of the GCSR as

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-492Local-Bus-to-VMEbus Enable Control Register This register is the map decoder en

xivCHAPTER 4 MCECC FunctionsIntroduction ...

2-50 Computer Group Literature Center Web SiteVMEchip22Local-Bus-to-VMEbus I/O Control Register This register controls the VMEbus short I/O map and th

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-512I2WP When this bit is high, write posting is enabled to the local bus F page. W

2-52 Computer Group Literature Center Web SiteVMEchip22A maximum of 4GB of data may be transferred with one DMAC command. Larger transfers can be acco

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-532.DMAC RegistersThis section provides addresses and bit level descriptions of th

2-54 Computer Group Literature Center Web SiteVMEchip22TBLSC These bits control the snoop signal lines on the local bus when the DMAC is table walking

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-5520 The request level is 0. 1 The request level is 1. 2 The request level is 2. 3

2-56 Computer Group Literature Center Web SiteVMEchip22always requests at the old level until it becomes bus master and the new level takes effect. If

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-572DMAC Control Register 2 (bits 8-15) This portion of the control register is loa

2-58 Computer Group Literature Center Web SiteVMEchip22SNP These bits control the snoop signal lines on the local bus when the DMAC is local bus maste

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-592VMEbus address modifier bits 2-5, and address modifier bits 0 and 1 are provide

xvScrub Prescaler Counter (Bits 7-0)...4-24Scrub Timer Counter (Bits 15-8)...

2-60 Computer Group Literature Center Web SiteVMEchip22DMAC VMEbus Address Counter In direct mode, this counter is programmed with the starting addres

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-612VMEbus Interrupter Control Register This register controls the VMEbus interrup

2-62 Computer Group Literature Center Web SiteVMEchip22VMEbus Interrupter Vector Register This register controls the VMEbus interrupter vector. MPU St

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-632DMAIC The DMAC interrupt counter is incremented when an interrupt is sent to th

2-64 Computer Group Literature Center Web SiteVMEchip22DLPE If this bit is set, the DMAC has received a TEA and the status indicated a parity error du

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-652DMAC Ton/Toff Timers and VMEbus Global Time-out Control RegisterThis register c

2-66 Computer Group Literature Center Web SiteVMEchip22VME Access, Local Bus, and Watchdog Time-out Control Register WDTO These bits define the watchd

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-672Prescaler Control Register The prescaler provides the various clocks required b

2-68 Computer Group Literature Center Web SiteVMEchip22Tick Timer 1 Compare Register The tick timer 1 counter is compared to this register. When they

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-692Tick Timer 2 Compare Register The tick timer 2 counter is compared to this regi

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2-70 Computer Group Literature Center Web SiteVMEchip22Board Control Register RSWE The RESET switch enable bit is used with the “no VMEbus interface”

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-712Watchdog Timer Control Register WDEN When this bit is high, the watchdog timer

2-72 Computer Group Literature Center Web SiteVMEchip22WDCS When this bit is set high, the watchdog time-out status bit (WDTO bit in this register) is

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-732Tick Timer 1 Control Register EN When this bit is high, the counter increments.

2-74 Computer Group Literature Center Web SiteVMEchip22Programming the Local Bus InterrupterThe local bus interrupter is used by devices that need to

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-752Table 2-4. Local Bus Interrupter SummaryInterrupt VectorPriority for Simultane

2-76 Computer Group Literature Center Web SiteVMEchip22Notes1. X = The contents of vector base register 0. 2. Y = The contents of vector base register

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-772Local Bus Interrupter Status Register (bits 24-31) This register is the local b

2-78 Computer Group Literature Center Web SiteVMEchip22Local Bus Interrupter Status Register (bits 16-23) This register is the local bus interrupter s

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-792Local Bus Interrupter Status Register (bits 8-15) This register is the local bu

xviiList of FiguresFigure 1-1. MVME167P Block Diagram...1-5Figure 1-2. MVME177P Block

2-80 Computer Group Literature Center Web SiteVMEchip22Local Bus Interrupter Status Register (bits 0-7) This register is the local bus interrupter sta

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-812Local Bus Interrupter Enable Register (bits 24-31) This register is the local b

2-82 Computer Group Literature Center Web SiteVMEchip22Local Bus Interrupter Enable Register (bits 16-23) This register is the local bus interrupter e

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-832Local Bus Interrupter Enable Register (bits 8-15) This is the local bus interru

2-84 Computer Group Literature Center Web SiteVMEchip22Local Bus Interrupter Enable Register (bits 0-7) This is the local bus interrupter enable regis

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-852Software Interrupt Set Register (bits 8-15) This register is used to set the so

2-86 Computer Group Literature Center Web SiteVMEchip22CVI1E Clear VMEbus IRQ1 edge-sensitive interrupt. CPE Not used on MVME1x7P. CMWP Clear VMEbus m

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-872Interrupt Clear Register (bits 8-15) This register is used to clear the edge so

2-88 Computer Group Literature Center Web SiteVMEchip22Interrupt Level Register 1 (bits 16-23) This register is used to define the level of the SYSFAI

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-892Interrupt Level Register 1 (bits 0-7) This register is used to define the level

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2-90 Computer Group Literature Center Web SiteVMEchip22Interrupt Level Register 2 (bits 16-23) This register is used to define the level of the GCSR S

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-912Interrupt Level Register 2 (bits 0-7) This register is used to define the level

2-92 Computer Group Literature Center Web SiteVMEchip22Interrupt Level Register 3 (bits 16-23) This register is used to define the level of the softwa

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-932Interrupt Level Register 3 (bits 0-7) This register is used to define the level

2-94 Computer Group Literature Center Web SiteVMEchip22Interrupt Level Register 4 (bits 16-23) This register is used to define the level of the VMEbus

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-952Interrupt Level Register 4 (bits 0-7) This register is used to define the level

2-96 Computer Group Literature Center Web SiteVMEchip22I/O Control Register 1 This register is a general purpose I/O control register. Bits 16-19 cont

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-972I/O Control Register 2 GPIOO1 Connects to pin 16 of the Remote Status and Contr

2-98 Computer Group Literature Center Web SiteVMEchip22Miscellaneous Control Register DISBGN When this bit is high, the VMEbus BGIN filters are disabl

LCSR Programming Modelhttp://www.motorola.com/computer/literature 2-992from the retry and the board does not lose its turn on the VMEbus. For this rea

xixList of TablesTable 1-1. MVME1X7P Features Summary...1-3Table 1-2. Functions Duplicated

2-100 Computer Group Literature Center Web SiteVMEchip22GCSR Programming ModelThis section describes the programming model for the Global Control and

GCSR Programming Modelhttp://www.motorola.com/computer/literature 2-1012The Location Monitor Status register provides the status of the location monit

2-102 Computer Group Literature Center Web SiteVMEchip22Programming the GCSRA complete description of the GCSR appears in the following tables. Each r

GCSR Programming Modelhttp://www.motorola.com/computer/literature 2-1032Table 2-5 shows a summary of the GCSR. VMEchip2 Revision Register This registe

2-104 Computer Group Literature Center Web SiteVMEchip22VMEchip2 ID RegisterThis register is the VMEchip2 ID register. The ID for the VMEchip2 is 10.

GCSR Programming Modelhttp://www.motorola.com/computer/literature 2-1052SIG3 The SIG3 bit is set when a VMEbus master writes a 1 to it. When the SIG3

2-106 Computer Group Literature Center Web SiteVMEchip22VMEchip2 Board Status/Control Register This register is the VMEchip2 board status/control regi

GCSR Programming Modelhttp://www.motorola.com/computer/literature 2-1072General Purpose Register 0 This register is a general purpose register that al

2-108 Computer Group Literature Center Web SiteVMEchip22General Purpose Register 3 This register is a general purpose register that allows a local bus

3-133PCCchip2IntroductionThis chapter defines the peripheral channel controller ASIC, referred to hereafter as the PCCchip2. The PCCchip2 is designed

© Copyright 2000 Motorola, Inc.All rights reserved.Printed in the United States of America.Motorola® and the Motorola logo are registered trademarks o

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3-2 Computer Group Literature Center Web SitePCCchip23Functional DescriptionThe following sections provide an overview of the functions provided by th

Functional Descriptionhttp://www.motorola.com/computer/literature 3-33BBRAM InterfaceThe PCCchip2 provides a read/write interface to the BBRAM by any

3-4 Computer Group Literature Center Web SitePCCchip23MPU Channel Attention access is used to cause the 82596CA to begin executing memory resident Com

Functional Descriptionhttp://www.motorola.com/computer/literature 3-53memory. The LANC Error Status Register in the PCCchip2 is updated and a LANC bus

3-6 Computer Group Literature Center Web SitePCCchip2353C710 SCSI Controller InterfaceThe PCCchip2 provides a map decoder and an interrupt handler for

Functional Descriptionhttp://www.motorola.com/computer/literature 3-73General Purpose I/O PinThe General Purpose I/O pin can be used as an input pin,

3-8 Computer Group Literature Center Web SitePCCchip23to the CD2401. Note that the PCCchip2 drives the CD2401 A7-A0 pins with $01 for modem interrupt

Functional Descriptionhttp://www.motorola.com/computer/literature 3-93Tick TimerThe PCCchip2 includes two 32-bit general purpose tick timers. The tick

3-10 Computer Group Literature Center Web SitePCCchip23Overall Memory MapThe following memory map includes all devices selected by the PCCchip2 map de

Programming Modelhttp://www.motorola.com/computer/literature 3-113Programming ModelThis section defines the programming model for the control and stat

xxiAbout This ManualThis manual provides board-level information and detailed ASIC information, including register bit descriptions, for the MVME167PA

3-12 Computer Group Literature Center Web SitePCCchip23Table 3-2. PCCchip2 Memory Map - Control and Status RegistersThis sheet continues on facing pa

Programming Modelhttp://www.motorola.com/computer/literature 3-133This sheet begins on facing page.INTERRUPTMASK LEVELINTERRUPTIPL LEVELTIC TIMER 2IRQ

3-14 Computer Group Literature Center Web SitePCCchip23Chip ID RegisterThe Chip ID Register is located at $FFF42000. It is an 8-bit read-only register

Programming Modelhttp://www.motorola.com/computer/literature 3-153General Control RegisterThe General Control Register is located at $FFF42002. It is

3-16 Computer Group Literature Center Web SitePCCchip23C040 CPU040. This bit should remain set to indicate that the MPU is from the M68000 family. Whe

Programming Modelhttp://www.motorola.com/computer/literature 3-173A normal read access to the Vector Base Register yields the value $0F if the read ha

3-18 Computer Group Literature Center Web SitePCCchip23A suggested setting of the Local Interrupt Vector Register in the SCC chip is $5C. This produce

Programming Modelhttp://www.motorola.com/computer/literature 3-193Tick Timer 1 CounterThe Tick Timer 1 Counter is a 32-bit read/write register located

3-20 Computer Group Literature Center Web SitePCCchip23Tick Timer 2 CounterThe Tick Timer 2 Counter is a 32-bit read/write register located at address

Programming Modelhttp://www.motorola.com/computer/literature 3-213frequency is used for BCLK. To provide a 1 MHz clock to the tick timers, the prescal

xxiiOverview of ContentsChapter 1, Programming Issues, describes the board-level hardware features of MVME1X7P single-board computers. It includes mem

3-22 Computer Group Literature Center Web SitePCCchip23Tick Timer 2 Control RegisterThis is an 8-bit read/write register that controls Tick Timer 2. I

Programming Modelhttp://www.motorola.com/computer/literature 3-233Tick Timer 1 Control RegisterThis is an 8-bit read/write register that controls Tick

3-24 Computer Group Literature Center Web SitePCCchip23General Purpose Input Interrupt Control RegisterIL2-IL0 These three bits select the interrupt l

Programming Modelhttp://www.motorola.com/computer/literature 3-253General Purpose Input/Output Pin Control RegisterGPO When GPO is set, and GPOE is se

3-26 Computer Group Literature Center Web SitePCCchip23INT Interrupt Status. When this bit is high a Tick Timer 2 interrupt is being generated at the

Programming Modelhttp://www.motorola.com/computer/literature 3-273SCC Error Status and Interrupt Control RegistersThis section provides addresses and

3-28 Computer Group Literature Center Web SitePCCchip23SCC Modem Interrupt Control RegisterIL2-IL0 Interrupt Request Level. These three bits select th

Programming Modelhttp://www.motorola.com/computer/literature 3-293SCC Transmit Interrupt Control RegisterIL2-IL0 Interrupt Request Level. These three

3-30 Computer Group Literature Center Web SitePCCchip23SCC Receive Interrupt Control RegisterIL2-IL0 Interrupt Request Level. These three bits select

Programming Modelhttp://www.motorola.com/computer/literature 3-313Modem PIACK RegisterThe Modem PIACK Register is used to execute modem pseudo interru

xxiiiYou can also submit comments to the following e-mail address: [email protected] all your correspondence, please list your name, posit

3-32 Computer Group Literature Center Web SitePCCchip23Transmit PIACK RegisterThe Transmit PIACK Register is used to execute transmit pseudo interrupt

Programming Modelhttp://www.motorola.com/computer/literature 3-333Receive PIACK RegisterThe Receive PIACK Register is used to execute receive pseudo i

3-34 Computer Group Literature Center Web SitePCCchip23LANC Error Status and Interrupt Control RegistersThis section provides addresses and bit level

Programming Modelhttp://www.motorola.com/computer/literature 3-35382596CA LANC Interrupt Control RegisterIL2-IL0 Interrupt Request Level. These three

3-36 Computer Group Literature Center Web SitePCCchip23LANC Bus Error Interrupt Control RegisterIL2-IL0 Interrupt Request Level. These three bits sele

Programming Modelhttp://www.motorola.com/computer/literature 3-373Programming the SCSI Error Status and Interrupt RegistersThis section provides addre

3-38 Computer Group Literature Center Web SitePCCchip23SCSI Interrupt Control RegisterIL2-IL0 Interrupt Request Level. These three bits select the int

Programming Modelhttp://www.motorola.com/computer/literature 3-393Programming the Printer PortThis section provides addresses and bit level descriptio

3-40 Computer Group Literature Center Web SitePCCchip23Printer FAULT Interrupt Control RegisterIL2-IL0 These three bits select the interrupt level for

Programming Modelhttp://www.motorola.com/computer/literature 3-413Printer SEL Interrupt Control RegisterIL2-IL0 These three bits select the interrupt

xxivboldis used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of program

3-42 Computer Group Literature Center Web SitePCCchip23Printer PE Interrupt Control RegisterIL2-IL0 These three bits select the interrupt level for th

Programming Modelhttp://www.motorola.com/computer/literature 3-433Printer BUSY Interrupt Control RegisterIL2-IL0 These three bits select the interrupt

3-44 Computer Group Literature Center Web SitePCCchip23Printer Input Status RegisterBSY This bit reflects the state of the Printer Busy input pin. It

Programming Modelhttp://www.motorola.com/computer/literature 3-453Printer Port Control RegisterMAN Manual Strobe Control - This bit selects the auto o

3-46 Computer Group Literature Center Web SitePCCchip23INP Printer Input Prime - This bit controls the input prime signal. When this bit is high, the

Programming Modelhttp://www.motorola.com/computer/literature 3-473Printer Data RegisterPD15-PD0 Writing to these bits causes the PCCchip2 to latch dat

3-48 Computer Group Literature Center Web SitePCCchip23Interrupt Priority Level RegisterIPL2-IPL0 Interrupt Priority Level - These bits reflect the pr

Programming Modelhttp://www.motorola.com/computer/literature 3-493Interrupt Mask Level RegisterMSK2-MSK0 Interrupt Mask Level - The interrupt mask lev

3-50 Computer Group Literature Center Web SitePCCchip23

4-144MCECC FunctionsIntroductionThe ECC DRAM Controller ASIC (MCECC) is a device used on earlier MVME167/177 models whose functions are now incorporat

xxvThe terms control bit, status bit, true, and false are used extensively in this document. The term control bit is used to describe a bit in a regis

4-2 Computer Group Literature Center Web SiteMCECC Functions4FeaturesMCECC functions now implemented on the Petra chip include:Table 4-1. MCECC Funct

Functional Descriptionhttp://www.motorola.com/computer/literature 4-34Functional DescriptionThe following sections provide an overview of the function

4-4 Computer Group Literature Center Web SiteMCECC Functions4Note The table is not complete because it cannot account for the effects of a write posti

Functional Descriptionhttp://www.motorola.com/computer/literature 4-54ECCThe Petra MCECC sector pair performs single-bit error correction and double-b

4-6 Computer Group Literature Center Web SiteMCECC Functions4Double Bit Error (Cycle Type = Burst Read or Non-Burst Read)You cannot correct the data t

Functional Descriptionhttp://www.motorola.com/computer/literature 4-744. Notify the local MPU via interrupt if so enabled. Triple (or Greater) Bit Err

4-8 Computer Group Literature Center Web SiteMCECC Functions4Error LoggingECC error logging is facilitated by the Petra MCECC sector because of its in

Functional Descriptionhttp://www.motorola.com/computer/literature 4-94ArbitrationThe MCECC sector has three different entities that can request use of

4-10 Computer Group Literature Center Web SiteMCECC Functions4Programming ModelThis section defines the programming model for the control and status r

Programming Modelhttp://www.motorola.com/computer/literature 4-114Table 4-3. MCECC Sector Internal Register Memory MapMCECC Sector Base Address = $FF

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4-12 Computer Group Literature Center Web SiteMCECC Functions4Register Register Bit Names Offset Name D31 D30 D29 D28 D27 D26 D25 D24$40 SCRUB PRESCAL

Programming Modelhttp://www.motorola.com/computer/literature 4-134Chip ID RegisterThe Chip ID register is hard-wired to a hexadecimal value of $81. Th

4-14 Computer Group Literature Center Web SiteMCECC Functions4Memory Configuration RegisterMSIZ2-MSIZ0MSIZ2-MSIZ0 together define the size of the tota

Programming Modelhttp://www.motorola.com/computer/literature 4-154Base Address RegisterThese eight bits are combined with the two most significant bit

4-16 Computer Group Literature Center Web SiteMCECC Functions4NCEBEN Setting the NCEBEN control bit enables the MCECC pair to assert TEA∗ when a non-c

Programming Modelhttp://www.motorola.com/computer/literature 4-174Note This register is configured only during power-up-reset and is unchanged by soft

4-18 Computer Group Literature Center Web SiteMCECC Functions4The writing of checkbits causes the MCECC sector to perform a read-modify-write to DRAM.

Programming Modelhttp://www.motorola.com/computer/literature 4-194cleared during normal system operation. DERC also allows the write portion of a read

4-20 Computer Group Literature Center Web SiteMCECC Functions4SCRB This status bit reflects the state of the scrubber. When the scrubber is in the pro

Programming Modelhttp://www.motorola.com/computer/literature 4-214Chip Prescaler CounterThis register reflects the current value in the prescaler coun

1-111Programming IssuesIntroductionThe MVME167P and MVME177P single-board computers are complex boards that interface both to the VMEbus and the SCSI

4-22 Computer Group Literature Center Web SiteMCECC Functions4STON2-STON0STON2-STON0 control the amount of time that the scrubber occupies the DRAM be

Programming Modelhttp://www.motorola.com/computer/literature 4-234Note that if STON2-0 is zero, the scrubber always releases the DRAM after one memory

4-24 Computer Group Literature Center Web SiteMCECC Functions4Scrub Prescaler Counter (Bits 7-0)This register reflects the current value in the scrub

Programming Modelhttp://www.motorola.com/computer/literature 4-254Scrub Timer Counter (Bits 7-0)This register reflects the current value in the Scrub

4-26 Computer Group Literature Center Web SiteMCECC Functions4Scrub Address Counter (Bits 23-16)This register reflects the current value in the Scrub

Programming Modelhttp://www.motorola.com/computer/literature 4-274Error Logger RegisterSBE SINGLE BIT ERROR is set when the last error logged was due

4-28 Computer Group Literature Center Web SiteMCECC Functions4ERRLOG When set, ERRLOG indicates that a single- or a double-bit error has been logged b

Programming Modelhttp://www.motorola.com/computer/literature 4-294Error Address (Bits 15-8)This register reflects the value that was on bits 15-8 of t

4-30 Computer Group Literature Center Web SiteMCECC Functions4Error Syndrome RegisterS6-S0 Bits SYNDROME6-0 reflect the syndrome value at the last log

Programming Modelhttp://www.motorola.com/computer/literature 4-314The states of RSIZ2-0 after reset (power-up, soft, or local) match those of the RSIZ

1-2 Computer Group Literature Center Web SiteProgramming Issues1The Petra ASIC is functionally compatible with each of the components that it replaces

4-32 Computer Group Literature Center Web SiteMCECC Functions4being set. The state of FSTRD after a reset (power-up, soft, or local) is determined by

Programming Modelhttp://www.motorola.com/computer/literature 4-334SDRAM Configuration Register SDCFG2-SDCFG0 Define the physical SDRAM memory populati

4-34 Computer Group Literature Center Web SiteMCECC Functions4InitializationMost DRAM vendors require that the DRAMs be subjected to some number of ac

Programming Modelhttp://www.motorola.com/computer/literature 4-3549. Ensure that the zero-fill stops after one pass by clearing the SCRBEN bit in the

4-36 Computer Group Literature Center Web SiteMCECC Functions4Syndrome DecodingThe following table defines the syndrome bit encoding for the Petra/MCE

Syndrome Decodinghttp://www.motorola.com/computer/literature 4-374Since the memory architecture is 32 data bits plus seven syndrome bits with a non-in

4-38 Computer Group Literature Center Web SiteMCECC Functions4

AA-1ASummary of ChangesIntroductionThis appendix summarizes the modifications that accompanied the introduction of the Petra ASIC on the MVME167P and

A-2 Computer Group Literature Center Web SiteSummary of ChangesA

BB-1BPrinter and Serial PortConnectionsIntroductionThis appendix has connection diagrams for the printer port and the four serial ports on the MVME1X7

Introductionhttp://www.motorola.com/computer/literature 1-31FeaturesThe “Petra” ASIC supplants the MCECC memory controller ASIC on MVME1X7P boards, pe

B-2 Computer Group Literature Center Web SitePrinter and Serial Port ConnectionsBFigure B-1. MVME1X7P Printer Port with MVME712M1347 9403MVME167P / M

Connection Diagramshttp://www.motorola.com/computer/literature B-3BFigure B-2. MVME1X7P Serial Port 1 Configured as DCE1348 9403MVME167P / MVME177PP2

B-4 Computer Group Literature Center Web SitePrinter and Serial Port ConnectionsBFigure B-3. MVME1X7P Serial Port 2 Configured as DCEMC145406DC27403R

Connection Diagramshttp://www.motorola.com/computer/literature B-5BFigure B-4. MVME1X7P Serial Port 3 Configured as DCEMC145406DA19413RXDMC145406DA23

B-6 Computer Group Literature Center Web SitePrinter and Serial Port ConnectionsBFigure B-5. MVME1X7P Serial Port 4 Configured as DCEMC145406DA25423R

Connection Diagramshttp://www.motorola.com/computer/literature B-7BFigure B-6. MVME1X7P Serial Port 1 Configured as DTE1352 9403MVME167P / MVME177PP2

B-8 Computer Group Literature Center Web SitePrinter and Serial Port ConnectionsBFigure B-7. MVME1X7P Serial Port 2 Configured as DTEMC145406DC27402T

Connection Diagramshttp://www.motorola.com/computer/literature B-9BFigure B-8. MVME1X7P Serial Port 3 Configured as DTEMC145406DA19412TXDMC145406DA23

B-10 Computer Group Literature Center Web SitePrinter and Serial Port ConnectionsBFigure B-9. MVME1X7P Serial Port 4 Configured as DTEMC145406DA25422

CC-1CRelated DocumentationMCG DocumentsThe Motorola Computer Group publications listed below are referenced in this manual. You can obtain paper or el

Safety SummaryThe following general safety precautions must be observed during all phases of operation, service, and repair of thisequipment. Failure

1-4 Computer Group Literature Center Web SiteProgramming Issues1Applicable Industry StandardsThese boards conform to the requirements of the following

C-2 Computer Group Literature Center Web SiteRelated DocumentationCManufacturers’ DocumentsFor additional information, refer to the following table fo

Related Specificationshttp://www.motorola.com/computer/literature C-3CRelated SpecificationsFor additional information, refer to the following table f

C-4 Computer Group Literature Center Web SiteRelated DocumentationCORMicroprocessor system bus for 1 to 4 byte dataBureau Central de la Commission Ele

IN-1IndexNumerics53C710 SCSI controller 1-15, 3-682596CALAN coprocessor 1-14, 3-3LAN coprocessor memory map 1-40LANC Interrupt Control Register 3-35AA

IndexIN-2 Computer Group Literature Center Web SiteINDEXBBack Off signal (PCCchip2 ASIC) 3-5backward compatibility 1-2base address, VMEchip2 LCSR 2-20

http://www.motorola.com/computer/literature IN-3INDEXclear-on-compare mode, VMEchip2 counters2-15clocks for VMEchip2 counters and timers2-67command ch

IndexIN-4 Computer Group Literature Center Web SiteINDEXEECC (error-correcting code) 4-5edge/level-sensitiveinterrupt, GPIO 3-24LANC 3-35printer ackno

http://www.motorola.com/computer/literature IN-5INDEXID register, VMEchip2 2-104VMEchip2 Board Status/Controlregister 2-106VMEchip2 ID register 2-104V

IndexIN-6 Computer Group Literature Center Web SiteINDEXInterrupt Priority Level register (PCCchip2ASIC) 3-48interrupt sourcesPCCchip2 VBR 3-17VMEchip

http://www.motorola.com/computer/literature IN-7INDEXlocal bus interrupter registersI/O Control register 1 2-96I/O Control register 2 2-97I/O Control

Introductionhttp://www.motorola.com/computer/literature 1-51Figure 1-1. MVME167P Block Diagram2816 0800VMEchip 2VMEbusInterfaceEPROM4 44-pinPLCC53C71

IndexIN-8 Computer Group Literature Center Web SiteINDEXDefaults register 2 4-32DRAM Control register 4-15Error Address (bits 23-16) 4-28Error Address

http://www.motorola.com/computer/literature IN-9INDEXnon-privileged access cycles, VMEbus 2-34,2-37Non-Volatile RAM (NVRAM) 1-3memory map 1-41see BBRA

IndexIN-10 Computer Group Literature Center Web SiteINDEXPrinter Input Status register (PCCchip2ASIC) 3-44Printer PE Interrupt Control register(PCCchi

http://www.motorola.com/computer/literature IN-11INDEXSCC Receive Interrupt Control register(PCCchip2 ASIC) 3-30SCC Transmit Interrupt Control registe

IndexIN-12 Computer Group Literature Center Web SiteINDEXTTEA source 3-34Tick Timer 1 Compare register 3-18Tick Timer 1 Control register (PCCchip2ASIC

http://www.motorola.com/computer/literature IN-13INDEXslave 2-9slave map decoders 2-26slave map decoders, programming 2-26system controller function 2

IndexIN-14 Computer Group Literature Center Web SiteINDEX

1-6 Computer Group Literature Center Web SiteProgramming Issues1Figure 1-2. MVME177P Block Diagram2816 0800VMEchip 2VMEbusInterfaceEPROM2 44-pinPLCC5

Programming Interfaceshttp://www.motorola.com/computer/literature 1-71Programming InterfacesThe following sections describe the programming interface

1-8 Computer Group Literature Center Web SiteProgramming Issues1As a general rule, any master can access any slave; not all combinations pass the comm

Programming Interfaceshttp://www.motorola.com/computer/literature 1-91MVME177The EEPROMs on the MVME177 share 2MB of memory with the first 2MB of Flas

1-10 Computer Group Literature Center Web SiteProgramming Issues1Figure 1-3. MVME177 Flash and EPROM Memory Mapping SchemesSRAMThe MVME167P and MVME1

Programming Interfaceshttp://www.motorola.com/computer/literature 1-111The MVME177P implements primary and secondary backup sources. You can select fr

1-12 Computer Group Literature Center Web SiteProgramming Issues1Battery-Backed-Up RAM and ClockAlthough the M48T58-70 RAM and clock chip is an 8-bit

Programming Interfaceshttp://www.motorola.com/computer/literature 1-131Serial Port InterfaceThe CD2401 serial controller chip (SCC) is used to impleme

FlammabilityAll Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers.EMI Caution!

1-14 Computer Group Literature Center Web SiteProgramming Issues1The CD2401 supports DMA operations to local memory. Because the CD2401 does not suppo

Programming Interfaceshttp://www.motorola.com/computer/literature 1-151Ethernet InterfaceThe MVME1X7P uses the Intel 82596CA LAN coprocessor to implem

1-16 Computer Group Literature Center Web SiteProgramming Issues1SCSI InterfaceThe MVME167P and MVME177P single-board computers provide for mass stora

Functional Descriptionhttp://www.motorola.com/computer/literature 1-171Watchdog TimerThe VMEchip2 ASIC supplies a watchdog timer function. When enable

1-18 Computer Group Literature Center Web SiteProgramming Issues1VMEbus Interface and VMEchip2The local-bus-to-VMEbus interface and the VMEbus-to-loca

Functional Descriptionhttp://www.motorola.com/computer/literature 1-191Notes1.RESET switch control.2. Watchdog timer control.3. Access and watchdog ti

1-20 Computer Group Literature Center Web SiteProgramming Issues18. 32-bit prescaler. The prescaler can also be accessed at $FFF40064 when the optiona

Memory Mapshttp://www.motorola.com/computer/literature 1-211The onboard I/O space must be marked cache-inhibit and serialized in its page table. Table

1-22 Computer Group Literature Center Web SiteProgramming Issues1($00000000 - $003FFFFF). The VMEchip2 and DRAM map decoders are disabled by a local b

Memory Mapshttp://www.motorola.com/computer/literature 1-231$FFF43100 - $FFF431FF Petra/MCECC #2 D8 256B 1$FFF43200 - $FFF43FFF Petra/MCECCs (repeated

CE Notice (European Community)Motorola Computer Group products with the CE marking comply with the EMC Directive (89/336/EEC). Compliance with this di

1-24 Computer Group Literature Center Web SiteProgramming Issues1Notes1. For a complete description of the register bits, refer to the data sheet for

Memory Mapshttp://www.motorola.com/computer/literature 1-251Detailed I/O Memory MapsTables 1-5 through 1-14 give the detailed memory maps for: 7 You

1-26 Computer Group Literature Center Web SiteProgramming Issues1Table 1-5. VMEchip2 Memory Map (Sheet 1 of 3)DMA TBSNP MODEROMZEROSRAMSPEEDADDER2SLA

Memory Mapshttp://www.motorola.com/computer/literature 1-271This sheet begins on facing page.ARBROBNMASTDHBMASTDWBMSTFAIRMSTRWDMASTERVMEBUSDMAHALTDMAE

1-28 Computer Group Literature Center Web SiteProgramming Issues1Table 1-5. VMEchip2 Memory Map (Sheet 2 of 3)ENIRQ31ENIRQ30ENIRQ29ENIRQ28ENIRQ27ENIR

Memory Mapshttp://www.motorola.com/computer/literature 1-291This sheet begins on facing page.0123456789101112131415VMEACCESSTIMERLOCALBUSTIMERWD TIME

1-30 Computer Group Literature Center Web SiteProgramming Issues1Table 1-5. VMEchip2 Memory Map (Sheet 3 of 3) VMEchip2 GCSR Base Address = $FFF40100

Memory Mapshttp://www.motorola.com/computer/literature 1-311Table 1-6. Printer Memory MapPrinter ACK Interrupt Control Register $FFF42030BIT31302

1-32 Computer Group Literature Center Web SiteProgramming Issues1Table 1-7. PCCchip2 Memory MapPRTRFLTPLTYPRTRFLTE/L*PRTRFLTINTPRTRFLTIENPRTRFLTICLRP

Memory Mapshttp://www.motorola.com/computer/literature 1-331INTERRUPTMASK LEVELINTERRUPTIPL LEVELTIC TIMER 2IRQ LEVELSCC TRANSMITIRQ LEVELCLROVF1COCEN

Limited and Restricted Rights LegendIf the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following n

1-34 Computer Group Literature Center Web SiteProgramming Issues1Table 1-8. MCECC Internal Register Memory MapMCECC Base Address = $FFF43000 (1st); $

Memory Mapshttp://www.motorola.com/computer/literature 1-351$48 SCRUB TIMERST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0$4C SCRUB ADDR CNTR0 0 0 0 0 SAC26 SAC25 SAC

1-36 Computer Group Literature Center Web SiteProgramming Issues1Table 1-9. Cirrus Logic CD2401 Serial Port Memory MapBase Address = $FFF45000Registe

Memory Mapshttp://www.motorola.com/computer/literature 1-371Bit Rate and Clock Option RegistersReceive Frame Address Register1 RFAR1 1F B R/W SyncRece

1-38 Computer Group Literature Center Web SiteProgramming Issues1Receive Interrupt Status Register low RISRl 89 B RReceive Interrupt Status Register h

Memory Mapshttp://www.motorola.com/computer/literature 1-391B Receive Buffer Byte Count BRBCNT 48 W R/WA Receive Buffer Status ARBSTS 4F B R/WB Receiv

1-40 Computer Group Literature Center Web SiteProgramming Issues1Note This is a 16-bit registerNotes 1. Refer to the MPU Port and MPU Channel Attentio

Memory Mapshttp://www.motorola.com/computer/literature 1-411Note Accesses may be 8-bit or 32-bit, but not 16-bit. BBRAM/TOD Clock Memory MapThe M48T58

1-42 Computer Group Literature Center Web SiteProgramming Issues1used by the MVME1X7P board debugger (MVME1X7Bug). The fifth area, detailed in Table 1

Memory Mapshttp://www.motorola.com/computer/literature 1-431Notes W = Write BitR = Read Bit S = Sign Bit ST = Stop Bit FT = Frequency Test x = Must be

viiContentsAbout This ManualOverview of Contents ...xxiiCo

1-44 Computer Group Literature Center Web SiteProgramming Issues1struct brdi_cnfg {char version[4];char serial[12];char id[16];char pwa[16];char speed

Memory Mapshttp://www.motorola.com/computer/literature 1-451structure for that set. For example, for a 64MB, 33MHz MVME167P board at revision C, the P

1-46 Computer Group Literature Center Web SiteProgramming Issues115. The final byte of the area is reserved for a checksum (as defined in the Debuggin

Interrupt Handlinghttp://www.motorola.com/computer/literature 1-471Interrupt HandlingM68000-based systems use hardware-vectored interrupts. Board MPUs

1-48 Computer Group Literature Center Web SiteProgramming Issues11. Set up Tick Timer: 2. Set up local bus interrupter:Step Register and Address Actio

Cache Coherency (MVME167P)http://www.motorola.com/computer/literature 1-491Periodic Tick Timer 1 interrupts now occur, so you need an interrupt handle

1-50 Computer Group Literature Center Web SiteProgramming Issues1ensure that data shared by multiple processors is kept in un-cached memory. The softw

Using Bus Timershttp://www.motorola.com/computer/literature 1-511Using Bus TimersThis section illustrates the use of bus timers by describing the sequ

1-52 Computer Group Literature Center Web SiteProgramming Issues1DS1 goes inactive). This time should be longer than any expected legitimate transfer

Supervisor Stack Pointer (MC68060)http://www.motorola.com/computer/literature 1-531Note Software emulation of CAS2 and misaligned CAS instructions is

viiiFunctional Description ...1-17VMEbus Interface and VMEchi

1-54 Computer Group Literature Center Web SiteProgramming Issues1Sources of Local Bus ErrorsA TEA* signal (indicating a bus error) is returned to the

Error Conditionshttp://www.motorola.com/computer/literature 1-551❏ A hardware error occurs on the VMEbus.❏ A VMEbus slave reports an access error (suc

1-56 Computer Group Literature Center Web SiteProgramming Issues1MPU Parity ErrorMPU Offboard ErrorMPU TEA - Cause UnidentifiedDescription: A DRAM par

Error Conditionshttp://www.motorola.com/computer/literature 1-571MPU Local Bus Time-outDMAC VMEbus ErrorDMAC Parity ErrorDescription: An error occurre

1-58 Computer Group Literature Center Web SiteProgramming Issues1DMAC Offboard ErrorDMAC LTO ErrorDescription: Error encountered while the Local Bus s

Error Conditionshttp://www.motorola.com/computer/literature 1-591DMAC TEA - Cause UnidentifiedSCC Retry ErrorDescription: An error occurred while the

1-60 Computer Group Literature Center Web SiteProgramming Issues1SCC Parity ErrorSCC Offboard ErrorDescription: Parity Error detected while the SCC wa

Error Conditionshttp://www.motorola.com/computer/literature 1-611SCC LTO ErrorLAN Parity ErrorLAN Offboard ErrorDescription: Local Bus Time-out occurr

1-62 Computer Group Literature Center Web SiteProgramming Issues1LAN LTO ErrorSCSI Parity ErrorSCSI Offboard ErrorDescription: Local Bus Time-out occu

Error Conditionshttp://www.motorola.com/computer/literature 1-631SCSI LTO ErrorDescription: Local Bus Time-out occurred while the 53C710 was Local Bu

ixLAN Offboard Error ...1-61LAN LTO Error ...

1-64 Computer Group Literature Center Web SiteProgramming Issues1

2-122VMEchip2IntroductionThis chapter describes the VMEchip2 ASIC, the local-bus/VMEbus interface chip. The VMEchip2 interfaces the local bus to the V

2-2 Computer Group Literature Center Web SiteVMEchip22VMEbus-to-Local-Bus InterfaceProgrammable VMEbus map decoderProgrammable AM decoderProgrammable

Introductionhttp://www.motorola.com/computer/literature 2-32VMEbus System ControllerArbiter with software-configured arbitration modes: – Priority (PR

2-4 Computer Group Literature Center Web SiteVMEchip22Functional BlocksThe following sections provide an overview of the functions implemented by the

Functional Blockshttp://www.motorola.com/computer/literature 2-52Figure 2-1. VMEchip2 Block Diagram1344 9403DATACONTROLADDRESSCONTROLDATACONTROLADDRE

2-6 Computer Group Literature Center Web SiteVMEchip22Using the four programmable map decoders, separate VMEbus maps can be created, each with its own

Functional Blockshttp://www.motorola.com/computer/literature 2-72have been accessed. This enhances the portability of software because it allows softw

2-8 Computer Group Literature Center Web SiteVMEchip22The requester requests the bus if any of the following conditions occur: 1. The local bus master

Functional Blockshttp://www.motorola.com/computer/literature 2-92VMEbus-to-Local-Bus InterfaceThe VMEbus-to-local-bus interface allows an off-board VM